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please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 1 post office box 1443 ? houston, texas 772511443 high-performance static cmos technology includes the t320c2xlp core cpu object compatible with the tms320c2xx source code compatible with tms320c25 upwardly compatible with tms320c5x 132-pin plastic quad flat package (pq suffix) 50-ns instruction cycle time industrial and automotive temperature available memory 544 words 16 bits of on-chip data/program dual-access ram 16k words 16 bits of on-chip program rom ('c240)/flash eeprom ('f240) 224k words 16 bits of total memory address reach (64k data, 64k program and 64k i/o, and 32k global memory space) event-manager module 12 compare / pulse-width modulation (pwm) channels three 16-bit general-purpose timers with six modes, including continuous up and up / down counting three 16-bit full-compare units with deadband three 16-bit simple-compare units four capture units (two with quadrature encoder-pulse interface capability) dual 10-bit analog-to-digital conversion module 28 individually programmable, multiplexed i / o pins phase-locked-loop (pll)-based clock module watchdog timer module (with real-time interrupt) serial communications interface (sci) module serial peripheral interface (spi) module six external interrupts (power drive protect, reset, nmi, and three maskable interrupts) four power-down modes for low-power operation scan-based emulation development tools available: texas instruments (ti ? ) ansi c compiler, assembler / linker, and c-source debugger scan-based self-emulation (xds510 ? ) third-party digital motor control and fuzzy-logic development support description the tms320c240 and tms320f240 devices are the first members of a new family of dsp controllers based on the tms320c2xx generation of 16-bit fixed-point digital signal processors (dsps). unless otherwise noted, the term 'x240 refers to both the tms320c240 and the tms320f240. table 1 provides a comparison of the features of each device. the only difference between these two devices is the type of program memory: the 'c240 contains 16k words of rom and the 'f240 contains 16k words of flash. this new family is optimized for digital motor/motion control applications. the dsp controllers combine the enhanced tms320 architectural design of the 'c2xlp core cpu for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. these peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 pwm outputs, and a dual10-bit analog-to-digital converter (adc), which can perform two simultaneous conversions within 6.1 m s. see the functional block diagram. copyright ? 1998, texas instruments incorporated ti and xds510 are trademarks of texas instruments incorporated. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 2 post office box 1443 ? houston, texas 772511443 contents introduction description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pq package (top view) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block diagram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . detailed description architectural overview 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system-level functions 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device memory map 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral memory map 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital i/o and shared pin functions 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description of group1 shared i/o pins 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description of group2 shared i/o pins 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital i/o control registers 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device reset and interrupts 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hardware-generated interrupts 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupts 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock generation 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block diagram of the tms320x240 dsp cpu 30 . . . . . . . . . . . . . . . 'x240 dsp core cpu 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . status and control registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . central processing unit 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input scaling shifter 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplier 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . central arithmetic logic unit 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . accumulator 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . auxiliary registers and auxiliary-register arithmetic unit (arau) 37 . . . . . . . . . internal memory 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dual-access ram (daram) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rom (tms320c240 only) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash eeprom (tms320f240 only) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash serial loader 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash control mode register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripherals 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external memory interface 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 3 post office box 1443 ? houston, texas 772511443 contents detailed description (continued) event-manager (ev) module 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose (gp) timers 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . full compare units 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmable-deadband generator 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . simple compares 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . compare/pwm waveform generation 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . compare/pwms characteristics 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture unit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . quadrature-encoder pulse (qep) circuit 43 . . . . . . . . . . . . . . . . . . . . . . . . . analog-to-digital converter (adc) module 43 . . . . . . . . . . . . . . . . . . . . . . . . . . serial peripheral interface (spi) module 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial communications interface (sci) module 47 . . . . . . . . . . . . . . . . . . . . . . watchdog (wd) and real-time interrupt (rti) module 49 . . . . . . . . . . . . . . . . scan-based emulation 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tms320x240 instruction set 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . addressing modes 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . repeat feature 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction set summary 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device and development-support tool nomenclature 59 . . . . . . . . . . . . . . . . documentation support 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical specifications absolute maximum ratings over operating free-air temperature range 61 . recommended operating conditions 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current variation with output voltage: spice simulation results 62 elec characteristics over recommended oper free-air temperature range 62 signal transition levels 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameter symbology 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general notes on timing parameters 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock options 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timings with the pll circuit disabled 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external reference crystal with pll-circuit-enabled clock option 67 . . . . . . . . . timings with the pll circuit enabled 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power mode timings 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 4 post office box 1443 ? houston, texas 772511443 contents electrical specifications (continued) memory and parallel i/o interface read timings 71 . . . . . . . . . . . . . . . . . . . . . . . memory and parallel i/o interface write timings 73 . . . . . . . . . . . . . . . . . . . . . . i/o timing variation with load capacitance: spice simulation results 75 . . . ready timings 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rs and poreset timings 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xf, bio , and mp/mc timings 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pwm/cmp timings 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture and qep timings 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt timings 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output timings 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial communications interface (sci) i/o timings 84 . . . . . . . . . . . . . . . . . . . . spi master mode external timing parameters (clock phase = 0) 85 . . . . . . . . spi master mode external timing parameters (clock phase = 1) 87 . . . . . . . . spi slave mode external timing parameters (clock phase = 0) 89 . . . . . . . . . spi slave mode external timing parameters (clock phase = 1) 91 . . . . . . . . . 10-bit dual analog-to-digital converter (adc) 93 . . . . . . . . . . . . . . . . . . . . . . . . . adc input pin circuit 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash eeprom 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming operation 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . erase operation 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash-write operation 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register file compilation 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package drawing, pq (s-pqfp-g***), plastic quad flatpack 104 . . . . . .
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 5 post office box 1443 ? houston, texas 772511443 pq package ( top view ) we w/r tms320c240 tms320f240 d7 d8 v ss dv dd d9 d10 d11 d12 d13 d14 d15 v ss tck tdi trst tms tdo rs ready mp/mc emu0 emu1/off nmi poreset reserved scirxd/io scitxd/io spisimo/io v ss dv dd spisomi/io spiclk/io wddis 2 d5 d4 d3 d6 d2 strb br r/w v dv ps d1 ss dd a5 a4 a3 v ss a2 a1 a0 tmrclk/iopb7 tmrdir/iopb6 t3pwm/t3cmp/iopb5 t2pwm/t2cmp/iopb4 t1pwm/t1cmp/iopb3 v ss dv dd pwm9/cmp9/iopb2 pwm8/cmp8/iopb1 pwm7/cmp7/iopb0 pwm6/cmp6 pwm5/cmp5 pwm4/cmp4 pwm3/cmp3 pwm2/cmp2 pwm1/cmp1 dv dd v ss adcin8/iopa3 adcin9/iopa2 adcin10 adcin11 v ssa v reflo v refhi v cca 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 10 8 6 7 v ss d0 cv ss cv dd is ds a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 v ss 58 52 53 54 55 51 56 59 60 67 62 63 61 64 69 57 68 65 66 70 71 72 73 74 75 76 77 78 79 80 81 82 83 9 11 12 13 14 15 16 17 1 131 129 130 132 2 3 4 5 124 122 120 121 123 125 126 127 128 119 117 118 xtal1/clkin xtal2 oscbyp xint3/io xint2/io xint1 spiste/io cap1/qep1/iopc4 cap3/iopc6 cap4/iopc7 cap2/qep2/iopc5 bio/iopc3 xf/iopc2 clkout/iopc1 adcsoc/iopc0 adcin5 adcin7 adcin15 adcin6 adcin4 adcin3 adcin1/iopa1 adcin0/iopa0 adcin14 adcin12 adcin13 adcin2 v ss v ss v ss pdpint dv dd dv dd dv dd cv dd 2 for the tms320f240 devices, this pin is v ccp /wddis.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 6 post office box 1443 ? houston, texas 772511443 terminal functions terminal type 2 description name no. type 2 description external interface data/address signals a0 (lsb) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 (msb) 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 o/z parallel address bus a0 [least significant bit (lsb)] through a15 [most significant bit (msb)]. a15 a0 are multiplexed to address external data/program memory or i/o. a15 a0 are placed in high-impedance state when emu1/off is active low and hold their previous states in power-down modes. d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 (msb) 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 i/o/z parallel data bus d0 (lsb) through d15 (msb). d15 d0 are multiplexed to transfer data between the tms320x240 and external data/program memory and i/o space (devices). d15 d0 are placed in the high-impedance state when not outputting, when in power-down mode, when reset (rs ) is asserted, or when emu1/off is active low. external interface control signals ds ps is 129 131 130 o/z data, program, and i/o space select signals. ds , ps , and is are always high unless low-level asserted for communication to a particular external space. they are placed in the high-impedance state during reset, power down, and when emu1/off is active low. ready 36 i data ready. ready indicates that an external device is prepared for the bus transaction to be completed. if the device is not ready (ready is low), the processor waits one cycle and checks ready again. r/w 4 o/z read/write signal. r/w indicates transfer direction during communication to an external device. it is normally in read mode (high), unless low level is asserted for performing a write operation. it is placed in the high-impedance state during reset, power down, and when emu1/off is active low. strb 6 o/z strobe. strb is always high unless asserted low to indicate an external bus cycle. it is placed in the high-impedance state during reset, power down, and when emu1/off is active low. we 1 o/z write enable. the falling edge of we indicates that the device is driving the external data bus (d15 d0). data can be latched by an external device on the rising edge of we . we is active on all external program, data, and i/o writes. we goes in the high-impedance state following reset and when emu1/off is active low. w/r 132 o/z write/read. w / r is an inverted form of r/w and can connect directly to the output enable of external devices. w/r is placed in the high-impedance state following reset and when emu1/off is active low. 2 i = input, o = output, z = high impedance
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 7 post office box 1443 ? houston, texas 772511443 terminal functions (continued) terminal type 2 description name no. type 2 description external interface control signals (continued) br 5 o/z bus request. br is asserted during access of external global data memory space. br can be used to extend the data memory address space by up to 32k words. br goes in the high-impedance state during reset, power down, and when emu1/off is active low. wddis 3 50 i flash-programming voltage supply. if v ccp = 5 v, then write/erase can be made to the entire on-chip flash memory blockethat is, for programming the flash. if v ccp = 0 v, then write/erase of the flash memory is not allowed, thereby protecting the entire memory block from being overwritten. wddis also functions as a hardware watchdog disable. the watchdog timer is disabled when v ccp /wddis = 5 v and bit 6 in wdcr is set to 1. adc inputs (unshared) adcin2 74 i adcin3 75 i adcin4 76 i analog in p uts to the first adc adcin5 77 i analog inp u ts to the first adc adcin6 78 i adcin7 79 i adcin10 89 i adcin11 88 i adcin12 83 i analog in p uts to the second adc adcin13 82 i analog inp u ts to the second adc adcin14 81 i adcin15 80 i bit i/o and shared functions pins adcin0/iopa0 72 i/o bidirectional digital i/o. analog input to the first adc. adcin0/iopa0 is configured as a digital input by all device resets. adcin1/iopa1 73 i/o bidirectional digital i/o. analog input to the first adc. adcin1/iopa1 is configured as a digital input by all device resets. adcin9/iopa2 90 i/o bidirectional digital i/o. analog input to the second adc. adcin9/iopa2 is configured as a digital input by all device resets. adcin8/iopa3 91 i/o bidirectional digital i/o. analog input to the second adc. adcin8/iopa3 is configured as a digital input by all device resets. pwm7/cmp7/iopb0 100 i/o/z bidirectional digital i/o. simple compare/pwm 1 output. the state of pwm7/cmp7/iopb0 is determined by the simple compare/pwm and the simple action control register (sactr). it goes to the high-impedance state when unmasked pdpint goes active low. pwm7/cmp7/iopb0 is configured as a digital input by all device resets. pwm8/cmp8/iopb1 101 i/o/z bidirectional digital i/o. simple compare/pwm 2 output. the state of pwm8/cmp8/iopb1 is determined by the simple compare/pwm and the sactr. it goes to the high-impedance state when unmasked pdpint goes active low. pwm8/cmp8/iopb1 is configured as a digital input by all device resets. pwm9/cmp9/iopb2 102 i/o/z bidirectional digital i/o. simple compare/pwm 3 output. the state of pwm9/cmp9/iopb2 is determined by the simple compare/pwm and sactr. it goes to the high-impedance state when unmasked pdpint goes active low. pwm9/cmp9/iopb2 is configured as a digital input by all device resets. 2 i = input, o = output, z = high impedance 3 for the tms320f240 devices, this pin is v ccp / wddis .
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 8 post office box 1443 ? houston, texas 772511443 terminal functions (continued) terminal type 2 description name no. type 2 description bit i/o and shared functions pins (continued) t1pwm/t1cmp/ iopb3 105 i/o/z bidirectional digital i/o. timer 1 compare output. t1pwm/t1cmp/iopb3 goes to the high- impedance state when unmasked pdpint goes active low. this pin is configured as a digital input by all device resets. t2pwm/t2cmp/ iopb4 106 i/o/z bidirectional digital i/o. timer 2 compare output. t2pwm/t2cmp/iopb4 goes to the high- impedance state when unmasked pdpint goes active low. this pin is configured as a digital input by all device resets. t3pwm/t3cmp/ iopb5 107 i/o/z bidirectional digital i/o. timer 3 compare output. t3pwm/t3cmp/iopb5 goes to the high- impedance state when unmasked pdpint goes active low. this pin is configured as a digital input by all device resets. tmrdir/iopb6 108 i/o bidirectional digital i/o. direction signal for the timers. up-counting direction if tmrdir/iopb6 is low, down-counting direction if this pin is high. this pin is configured as a digital input by all device resets. tmrclk/iopb7 109 i/o bidirectional digital i/o. external clock input for general-purpose timers. this pin is configured as a digital input by all device resets. adcsoc/iopc0 63 i/o bidirectional digital i/o. external start of conversion input for adc. this pin is configured as a digital input by all device resets. cap1 / qep1/iopc4 67 i/o bidirectional digital i/o. capture 1 or qep 1 input. this pin is configured as a digital input by all device resets. cap2 / qep2/iopc5 68 i/o bidirectional digital i/o. capture 2 or qep 2 input. this pin is configured as a digital input by all device resets. cap3/iopc6 69 i/o bidirectional digital i/o. capture 3 input. this pin is configured as a digital input by all device resets. cap4/iopc7 70 i/o bidirectional digital i/o. capture 4 input. this pin is configured as a digital input by all device resets. xf / iopc2 65 i/o bidirectional digital i/o. external flag output (latched software-programmable signal). xf is used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. this pin is configured as an external flag output by all device resets. bio / iopc3 66 i/o bidirectional digital i/o. branch control input. bio is polled by the bioz instruction. if bio is low, the cpu executes a branch. if bio is not used , it should be pulled high. this pin is configured as a branch-control input by all device resets. clkout/iopc1 64 i/o bidirectional digital i/o. clock output. clock output is selected by the clksrc bits in the syscr register. this pin is configured as a dsp clock output by a power-on reset. serial communications interface (sci) and bit i/o pins scitxd/io 44 i/o sci asynchronous serial port transmit data, or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. scirxd/io 43 i/o sci asynchronous serial port receive data, or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. 2 i = input, o = output, z = high impedance
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 9 post office box 1443 ? houston, texas 772511443 terminal functions (continued) terminal type 2 description name no. type 2 description serial peripheral interface (spi) and bit i/o pins spisimo/io 45 i/o spi slave in, master out , or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. spisomi/io 48 i/o spi slave out, master in, or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. spiclk/io 49 i/o spi clock, or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. spiste/io 51 i/o spi slave transmit enable (optional), or general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. compare signals pwm1/cmp1 pwm2/cmp2 pwm3/cmp3 pwm4/cmp4 pwm5/cmp5 pwm6/cmp6 94 95 96 97 98 99 o/z compare units compare or pwm outputs. the state of these pins is determined by the compare/pwm and the full action control register (actr). cmp1 cmp6 go to the high- impedance state when unmasked pdpint goes active low, and when reset (rs ) is asserted. interrupt and miscellaneous signals rs 35 i/o reset input. rs causes the tms320x240 to terminate execution and sets pc = 0. when rs is brought to a high level, execution begins at location zero of program memory. rs affects (or sets to zero) various registers and status bits. mp/mc 37 i mp/mc (microprocessor/microcomputer) select. if mp/mc is low, internal program memory is selected. if it is high, external program memory is selected. nmi 40 i nonmaskable interrupt. when nmi is activated, the device is interrupted regardless of the state of the intm bit of the status register. nmi has programmable polarity. poreset 41 i power-on reset. poreset causes the tms320x240 to terminate execution and sets pc = 0. when poreset is brought to a high level, execution begins at location zero of program memory. poreset affects (or sets to zero) the same registers and status bits as rs . in addi- tion, poreset initializes the pll control registers. xint1 53 i external user interrupt no. 1 xint2/io 54 i/o external user interrupt no. 2. general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. xint3/io 55 i/o external user interrupt no. 3. general-purpose bidirectional i/o. this pin is configured as a digital input by all device resets. pdpint 52 i maskable power-drive protection interrupt. if pdpint is unmasked and it goes active low, the timer compare outputs immediately go to the high-impedance state. clock signals xtal2 57 o pll oscillator output. xtal2 is tied to one side of a reference crystal when the device is in pll mode (clkmd[1:0] = 1x, ckcr0.7 6). this pin can be left unconnected in oscillator bypass mode (oscbyp v il ). this pin goes in the high-impedance state when emu1/off is active low. xtal1/clkin 58 i/z pll oscillator input. xtal1/clkin is tied to one side of a reference crystal in pll mode (clkmd[1:0] = 1x, ckcr0.7 6), or is connected to an external clock source in oscillator bypass mode (oscbyp v il ). oscbyp 56 i bypass oscillator if low 2 i = input, o = output, z = high impedance
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 10 post office box 1443 ? houston, texas 772511443 terminal functions (continued) terminal type 2 description name no. type 2 description supply signals cv ss 8 i digital core logic ground reference v ss 3 14 20 29 46 59 i digital logic ground reference v ss 61 71 92 104 113 120 i digital logic gro u nd reference v ssa 87 i analog ground reference dv dd 2 13 21 47 i digital i/o logic su pp ly voltage dv dd 62 93 103 121 i digital i/o logic s u ppl y v oltage cv dd 7 i digital core logic su pp ly voltage cv dd 60 i digital core logic s u ppl y v oltage v cca 84 i analog supply voltage v refhi 85 i adc analog voltage reference high v reflo 86 i adc analog voltage reference low test signals tck 30 i ieee standard test clock. tck is normally a free-running clock signal with a 50% duty cycle. the changes on test-access port (tap) input signals (tms and tdi) are clocked into the tap controller, instruction register, or selected test data register of the 'c2xx core on the rising edge of tck. changes at the tap output signal (tdo) occur on the falling edge of tck. tdi 31 i ieee standard test data input (tdi). tdi is clocked into the selected register (instruction or data) on a rising edge of tck. tdo 34 o/z ieee standard test data output (tdo). the contents of the selected register (instruction or data) are shifted out of tdo on the falling edge of tck. tdo is in the high-impedance state when off is active low. tms 33 i ieee standard test mode select. this serial control input is clocked into the tap controller on the rising edge of tck. 2 i = input, o = output, z = high impedance
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 11 post office box 1443 ? houston, texas 772511443 terminal functions (continued) terminal type 2 description name no. type 2 description test signals (continued) trst 32 i ieee standard test reset. trst , when active low, gives the scan system control of the operations of the device. if this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. emu0 38 i/o/z emulator pin 0. when trst is driven low, emu0 must be high for activation of the /off condition. when trst is driven high, emu0 is used as an interrupt to or from the emulator system and is defined as input/output through the scan. emu1/off 39 i/o/z emulator pin 1/disable all outputs. when trst is driven high, emu1/off is used as an interrupt to or from the emulator system and is defined as input/output through jtag scan. when trst is driven low, this pin is configured as off . when emu1/off is active low, it puts all output drivers in the high-impedance state. off is used exclusively for testing and emulation purposes (not for multiprocessing applications); therefore, for off condition, the following conditions apply: trst = low, emu0 = high, emu1/off = low. reserved 42 i reserved for test. this pin has an internal pulldown and must be left unconnected for the 'f240. on the 'c240, this pin is a no connect. 2 i = input, o = output, z = high impedance
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 12 post office box 1443 ? houston, texas 772511443 functional block diagram 4 2 16 pdpint 4 4 9 41 7 quadrature encoder pulse (qep) capture/ units compare timers purpose general- manager event software wait-state generation external memory interface emulation test/ peripheral bus timer watchdog interface communications serial- interface peripheral serial- converter to-digital analog- dual 10-bit data bus 3 reset digital input/output interrupts 20 4 module system-interface module clock program bus b1/b2 daram b0 daram rom or flash eeprom 2 initialization interrupts control memory controller program cpu 'c2xx shifter product preg treg multiplier shifter output accumulator alu shifter input registers mapped memory- registers auxiliary registers control status/ arau register instruction 2 the 'c240 device contains rom; the 'f240 device contains flash eeprom.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 13 post office box 1443 ? houston, texas 772511443 description (continued) table 1. characteristics of the 'x240 dsp controllers on-chip memory (words) power cycle package tms320x240 devices ram rom flash eeprom power supply (v) cycle time (ns) package type pin count data data / prog prog prog (v) (ns) pin count tms320c240 288 256 16k 5 50 pq 132p tms320f240 288 256 16k 5 50 pq 132p architectural overview the functional block diagram provides a high-level description of each component in the 'x240 dsp controller. the tms320x240 devices are composed of three main functional units: a 'c2xx dsp core, internal memory, and peripherals. in addition to these three functional units, there are several system-level features of the 'x240 that are distributed. these system features include the memory map, device reset, interrupts, digital input/ output (i / o), clock generation, and low-power operation. system-level functions device memory map the tms320x240 implements three separate address spaces for program memory, data memory, and i / o. each space accommodates a total of 64k 16-bit words. within the 64k words of data space, the 256 to 32k words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global memory allocation register (greg). access to global memory is arbitrated using the global memory bus request (br ) signal. on the 'x240, the first 96 (0 5fh) data memory locations are either allocated for memory-mapped registers or are reserved. this memory-mapped register space contains various control and status registers including those for the cpu. all the on-chip peripherals of the 'x240 device are mapped into data memory space. access to these registers is made by the cpu instructions addressing their data-memory locations. figure 1 shows the memory map.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 14 post office box 1443 ? houston, texas 772511443 device memory map (continued) 0000 interrupts (external) 003f 0040 external fdff 0000 interrupts (on-chip) 003f 0040 0000 005f 0060 01ff fe00 ffff 02ff 0300 feff ff00 0200 03ff 0400 07ff reserved 7000 peripheral memory- mapped registers (system, wd, adc, spi, sci, interrupts, i/o) 73ff 7400 743f 7440 77ff 0000 external ff0e feff ff00 reserved reserved 4000 external 3fff fdff fe00 ffff feff ff00 reserved i/o hex 2 rom/flash memory includes address range 0000h003fh hex data hex 007f 0080 reserved hex 8000 external ffff 7800 7fff ff0f on-chip daram b0 (cnf = 1) or external (cnf = 0) on-chip rom 2 (flash eeprom) (8 x 2k segments) mp/mc = 1 microprocessor mode mp/mc = 0 microcomputer mode program program wait-state generator control register memory-mapped registers and reserved on-chip daram b2 on-chip daram b0 (cnf = 0) or reserved (cnf = 1) on-chip daram b1 0800 6fff illegal peripheral memory-mapped registers (event manager) on-chip daram b0 (cnf = 1) or external (cnf = 0) reserved illegal flash control mode register reserved ff10 ffff fffe figure 1. tms320x240 memory map
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 15 post office box 1443 ? houston, texas 772511443 peripheral memory map the tms320x240 system and peripheral control register frame contains all the data, status, and control bits to operate the system and peripheral modules on the device (excluding the event manager). global-memory allocation register 0000 0003 0004 0005 0000 memory-mapped registers and reserved 005f 0060 on-chip daram b2 02ff 0300 01ff 0200 03ff on-chip daram b1 0400 reserved 73ff peripheral frame 1 7400 77ff 7800 external ffff 7000 700f reserved 0007 emulation registers and reserved peripheral frame 2 reserved on-chip daram b0 (cnf = 0) reserved (cnf = 1) interrupt-mask register illegal system configuration and control registers watchdog timer and pll control registers illegal digital-i/o control registers illegal reserved reserved interrupt mask, vector and flag registers 0006 005f 007f 0080 07ff 7000 743f 7440 7010 701f 7020 702f 7030 703f 7040 704f 7050 705f 7060 706f 7070 707f 7080 708f 7090 709f 7400 740c 7411 741c 7420 7426 7427 742b 742c 7434 7435 743f interrupt flag register spi sci illegal external-interrupt registers adc general-purpose timer registers capture & qep registers compare, pwm, and deadband registers reserved 7fff 8000 illegal 0800 6fff illegal hex hex 70a0 73ff reserved reserved 741d 741f 740d 7410 figure 2. peripheral memory map
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 16 post office box 1443 ? houston, texas 772511443 digital i/o and shared pin functions the 'c240 has a total of 28 pins shared between primary functions and i/os. these pins are divided into two groups: group1 e primary functions shared with i/os belonging to dedicated i/o ports, port a, port b, and port c. group2 e primary functions belonging to peripheral modules which also have a built-in i/o feature as a secondary function (for example, sci, spi, external interrupts, and pll clock modules). description of group1 shared i/o pins the control structure for group1 type shared i/o pins is shown in figure 3. the only exception to this configuration is the clkout/iopc1 pin. in figure 3, each pin has three bits that define its operation: mux control bit e this bit selects between the primary function (1) and i/o function (0) of the pin. i/o direction bit e if the i/o function is selected for the pin (mux control bit is set to 0), this bit determines whether the pin is an input (0) or an output (1). i/o data bit e if the i/o function is selected for the pin (mux control bit is set to 0) and the direction selected is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. the mux control bit, i/o direction bit, and i/o data bit are in the i/o control registers. primary function pin (read/write) iop data bit in out 0 = input 1 = output 01 mux control bit 0 = i/o function 1 = primary function iop dir bit primary function or i/o pin when the mux control bit = 1, the primary function is selected in all cases except for the following pins: 1. xf/iopc2 (0 = primary function) 2. bio /iopc3 (0 = primary function) note: figure 3. shared pin configuration a summary of group1 pin configurations and associated bits is shown in table 2.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 17 post office box 1443 ? houston, texas 772511443 description of group1 shared i/o pins (continued) table 2. group1 shared pin configurations pin # mux control register pin function selected i/o port data and direction 2 pin # register (name.bit #) (crx.n = 1) (crx.n = 0) register data bit # dir bit # 72 ocra.0 adcin0 iopa0 padatdir 0 8 73 ocra.1 adcin1 iopa1 padatdir 1 9 90 ocra.2 adcin9 iopa2 padatdir 2 10 91 ocra.3 adcin8 iopa3 padatdir 3 11 100 ocra.8 pwm7/cmp7 iopb0 pbdatdir 0 8 101 ocra.9 pwm8/cmp8 iopb1 pbdatdir 1 9 102 ocra.10 pwm9/cmp9 iopb2 pbdatdir 2 10 105 ocra.11 t1pwm/t1cmp iopb3 pbdatdir 3 11 106 ocra.12 t2pwm/t2cmp iopb4 pbdatdir 4 12 107 ocra.13 t3pwm/t3cmp iopb5 pbdatdir 5 13 108 ocra.14 tmrdir iopb6 pbdatdir 6 14 109 ocra.15 tmrclk iopb7 pbdatdir 7 15 63 ocrb.0 adcsoc iopc0 pcdatdir 0 8 64 syscr.76 0 0 iopc1 pcdatdir 1 9 0 1 wdclk e e e 1 0 sysclk e e e 1 1 cpuclk e e e 65 ocrb.2 iopc2 xf pcdatdir 2 10 66 ocrb.3 iopc3 bio pcdatdir 3 11 67 ocrb.4 cap1/qep1 iopc4 pcdatdir 4 12 68 ocrb.5 cap2/qep2 iopc5 pcdatdir 5 13 69 ocrb.6 cap3 iopc6 pcdatdir 6 14 70 ocrb.7 cap4 iopc7 pcdatdir 7 15 2 valid only if the i/o function is selected on the pin.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 18 post office box 1443 ? houston, texas 772511443 description of group2 shared i/o pins group2 shared pins belong to peripherals that have built-in general-purpose i/o capability. control and configuration for these pins are achieved by setting the appropriate bits within the control and configuration registers of the peripherals. table 3 lists the group2 shared pins. table 3. group2 shared pin configurations pin # primary function register address peripheral module 43 scirxd scipc2 705eh sci 44 scitxd scipc2 705eh sci 45 spisimo spipc2 704eh spi 48 spisomi spipc2 704eh spi 49 spiclk spipc1 704dh spi 51 spiste spipc1 704dh spi 54 xint2 xint2cr 7078h external interrupts 55 xint3 xint3cr 707ah external interrupts digital i/o control registers table 4 lists the registers available to the digital i/o module. as with other 'x240 peripherals, the registers are memory-mapped to the data space. table 4. addresses of digital i/o control registers address register name 7090h ocra i/o mux control register a 7092h ocrb i/o mux control register b 7098h padatdir i/o port a data and direction register 709ah pbdatdir i/o port b data and direction register 709ch pcdatdir i/o port c data and direction register device reset and interrupts the tms320x240 software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. the 'x240 recognizes three types of interrupt sources: reset (hardware- or software-initiated) is unarbitrated by the cpu and takes immediate priority over any other executing functions. all maskable interrupts are disabled until the reset service routine enables them. hardware-generated interrupts are requested by external pins or by on-chip peripherals. there are two types: external interrupts are generated by one of five external pins corresponding to the interrupts xint1, xint2, xint3, pdpint, and nmi. the first four can be masked both by dedicated enable bits and by the cpu's interrupt mask register (imr), which can mask each maskable interrupt line at the dsp core. nmi, which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. it can be locked out only by an already executing nmi or a reset. peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager, spi, sci, watchdog / real-time interrupt (wd/rti), and adc. they can be masked both by enable bits for each event in each peripheral and by the cpu's imr, which can mask each maskable interrupt line at the dsp core.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 19 post office box 1443 ? houston, texas 772511443 device reset and interrupts (continued) software-generated interrupts for the 'x240 device include: the intr instruction. this instruction allows initialization of any 'x240 interrupt with software. its operand indicates to which interrupt vector location the cpu branches. this instruction globally disables maskable interrupts (sets the intm bit to 1). the nmi instruction. this instruction forces a branch to interrupt vector location 24h, the same location used for the nonmaskable hardware interrupt nmi. nmi can be initiated by driving the nmi pin low or by executing an nmi instruction. this instruction globally disables maskable interrupts. the trap instruction. this instruction forces the cpu to branch to interrupt vector location 22h. the trap instruction does not disable maskable interrupts (intm is not set to 1); therefore, when the cpu branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. an emulator trap. this interrupt can be generated with either an intr instruction or a trap instruction. reset the reset operation ensures an orderly startup sequence for the device. there are five possible causes of a reset, as shown in figure 4. three of these causes are internally generated; the other two causes, the rs and poreset pins, are controlled externally. signal reset to reset out to device watchdog timer reset software-generated reset illegal address reset reset (rs ) pin active power-on reset (poreset ) pin active figure 4. reset signals the five possible reset signals are generated as follows: watchdog timer reset. a watchdog-timer-generated reset occurs if the watchdog timer overflows or an improper value is written to either the watchdog key register or the watchdog control register. (note that when the device is powered on, the watchdog timer is automatically active.) software-generated reset. this is implemented with the system control register (syscr). clearing the reset0 bit (bit 14) or setting the reset1 bit (bit 15) causes a system reset. illegal address reset. the system and peripheral module control register frame address map contains unimplemented address locations in the ranges labeled illegal. any access to an address located in the illegal ranges generate an illegal-address reset. reset pin active. to generate an external reset pulse on the rs pin, a low-level pulse duration of as little as a few nanoseconds is usually effective; however, pulses of one sysclk cycle are necessary to ensure that the device recognizes the reset signal. power-on reset pin active. to generate a power-on reset pulse on the poreset pin, a low-level pulse of one sysclk cycle is necessary to ensure that the device recognizes the reset signal. once a reset source is activated, the external rs pin is driven (active) low for a minimum of eight sysclk cycles. this allows the tms320x240 device to reset external system components. additionally, if a brown-out condition (v cc < v cc min for several microseconds causing poreset to go low) occurs or the rs pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 20 post office box 1443 ? houston, texas 772511443 reset (continued) the occurrence of a reset condition causes the tms320x240 to terminate program execution and affects various registers and status bits. during a reset, ram contents remain unchanged, and all control bits that are affected by a reset are initialized to their reset state. in the case of a power-on reset, the pll control registers are initialized to zero. the program needs to recognize power-on resets and configure the pll for correct operation. after a reset, the program can check the power-on reset flag (porst flag, syssr.15), the illegal address flag (illadr flag, syssr.12), the software reset flag (swrst flag, syssr.10), and the watchdog reset flag (wdrst flag, syssr.9) to determine the source of the reset. a reset does not clear these flags. rs and poreset must be held low until the clock signal is valid and v cc is within the operating range. in addition, poreset must be driven low when v cc drops below the minimum operating voltage. hardware-generated interrupts all the hardware interrupt lines of the dsp core are given a priority rank from 1 to 10 (1 being highest). when more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets acknowledged first. the others are acknowledged in order after that. of those ten lines, six are for maskable interrupt lines (int1int6) and one is for the nonmaskable interrupt (nmi) line. int1int6 and nmi have the priorities shown in table 5. table 5. interrupt priorities at the level of the dsp core interrupt priority at the dsp core reset 1 ti reserved 2 2 nmi 3 int1 4 int2 5 int3 6 int4 7 int5 8 int6 9 ti reserved 2 10 2 ti reserved means that the address space is reserved for texas instruments. the inputs to these lines are controlled by the system module and the event manager as summarized in table 6 and shown in figure 5. table 6. interrupt lines controlled by the system module and event manager peripheral interrupt lines system module int1 int5 int6 nmi event manager int2 int3 int4
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 21 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) dsp core 5 intc intb inta address lines 51 int6 int5 int4 int3 int2 int1 nmi address lines 51 system module event manager iack int6 int5 int4 int3 int2 int1 nmi iack nc nc nc figure 5. dsp interrupt structure at the level of the system module and the event manager, each of the maskable interrupt lines (int1int6) is connected to multiple maskable interrupt sources. sources connected to interrupt line int1 are called level 1 interrupts; sources connected to interrupt line int2 are called level 2 interrupts; and so on. for each interrupt line, the multiple sources also have a set priority ranking. the source with the highest priority has its interrupt request responded to by the dsp core first. figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. for each interrupt chain, the interrupt source of highest priority is at the top. priority decreases from the top of the chain to the bottom. figure 7 shows the interrupt sources and priority ranking for the event manager interrupts.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 22 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) iack1 irq1 iack5 irq5 iack6 irq6 nmi int1 int6 system-module external interrupt nmi to dsp int6 to dsp int1 to dsp nmi nc = no connection iack = interrupt acknowledge irq = interrupt request legend: system-module external interrupt xint1 (high priority) system-module external interrupt xint2 (high priority) system-module external interrupt xint3 (high priority) spi interrupt (high priority) sci receiver interrupt (low priority) spi interrupt (low priority) system-module external interrupt xint1 (low priority) system-module external interrupt xint2 (low priority) system-module external interrupt xint3 (low priority) dual adc interrupt iack_nmi irq_nmi iack2 irq2 iack3 irq3 iack4 irq4 nc nc nc nc nc nc int5 to dsp int5 int2 int3 int4 nc nc nc watchdog timer interrupt sci transmitter interrupt (low priority) sci receiver interrupt (high priority) sci transmitter interrupt (high priority) system module figure 6. system-module interrupt structure
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 23 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) iacka irqa iackb irqb iackc irqc inta intb intc power-drive protection interrupt compare1 interrupt compare 2 interrupt compare 3 interrupt simple- compare 1 interrupt simple- compare 2 interrupt simple- compare 3 interrupt timer 1 period interrupt timer 1 compare interrupt timer 1 underflow interrupt timer 1 overflow interrupt timer 2 period interrupt timer 2 compare interrupt timer 2 underflow interrupt timer 2 overflow interrupt timer 3 period interrupt timer 3 compare interrupt timer 3 underflow interrupt timer 3 overflow interrupt capture 1 interrupt capture 2 interrupt capture 3 interrupt capture 4 interrupt to dsp int4 to dsp int3 to dsp int2 iack = interrupt acknowledge irq = interrupt request legend: event manager figure 7. event-manager interrupt structure
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 24 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) each of the interrupt sources has its own control register with a flag bit and an enable bit. when an interrupt request is received, the flag bit in the corresponding control register is set. if the enable bit is also set, a signal is sent to arbitration logic, which can simultaneously receive similar signals from one or more of the other control registers. the arbitration logic compares the priority level of competing interrupt requests, and it passes the interrupt of highest priority to the cpu. the corresponding flag is set in the interrupt flag register (ifr), indicating that the interrupt is pending. the cpu then must decide whether to acknowledge the request. maskable hardware interrupts are acknowledged only after certain conditions are met: priority is highest. when more than one hardware interrupt is requested at the same time, the 'x240 services them according to the set priority ranking. intm bit is 0. the interrupt mode (intm) bit, bit 9 of status register st0, enables or disables all maskable interrupts: when intm = 0, all unmasked interrupts are enabled. when intm = 1, all unmasked interrupts are disabled. intm is set to 1 automatically when the cpu acknowledges an interrupt (except when initiated by the trap instruction) and at reset. it can be set and cleared by software. imr mask bit is 1. each of the maskable interrupt lines has a mask bit in the interrupt mask register (imr). to unmask an interrupt line, set its imr bit to 1. when the cpu acknowledges a maskable hardware interrupt, it jams the instruction bus with the intr instruction. this instruction forces the pc to the appropriate address from which the cpu fetches the software vector. this vector leads to an interrupt service routine. usually, the interrupt service routine reads the peripheral-vector-address offset from the peripheral-vector- address register (see table 7) to branch to code that is meant for the specific interrupt source that initiated the interrupt request. the 'x240 includes a phantom-interrupt vector offset (0000h), which is a system interrupt integrity feature that allows a controlled exit from an improper interrupt sequence. if the cpu acknowledges a request from a peripheral when, in fact, no peripheral has requested an interrupt, the phantom-interrupt vector is read from the interrupt-vector register. table 7 summarizes the interrupt sources, overall priority, vector address/offset, source, and function of each interrupt available on the tms320x240.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 25 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) table 7. 'x240 interrupt locations and priorities interrupt name overall priority dsp-core interrupt, and address peripheral vector address peripheral vector address offset maskable? 'x240 source peripheral module function interrupt rs 1 highest rs 0000h n/a n core, sd external, system reset (reset) reserved 2 int7 0026h n/a n/a n dsp core emulator trap nmi 3 nmi 0024h n/a 0002h n core, sd external user interrupt xint1 xint2 xint3 4 5 6 0001h 0011h 001fh y sd high-priority external user interrupts spiint 7 int1 0002h sysivr 0005h y spi high-priority spi interrupt rxint 8 0002h (system) sysivr (701eh) 0006h y sci sci receiver interrupt (high priority) txint 9 (system) 0007h y sci sci transmitter interrupt (high priority) wdtint 10 0010h y wdt watchdog timer interrupt pdpint 11 0020h y external power-drive protection int. cmp1int 12 0021h y ev.cmp1 full compare 1 interrupt cmp2int 13 0022h y ev.cmp2 full compare 2 interrupt cmp3int 14 0023h y ev.cmp3 full compare 3 interrupt scmp1int 15 int2 0004h 0024h y ev.cmp4 simple compare 1 interrupt scmp2int 16 0004h (event evivra (7432h) 0025h y ev.cmp5 simple compare 2 interrupt scmp3int 17 manager group a) 0026h y ev.cmp6 simple compare 3 interrupt tpint1 18 0027h y ev.gpt1 timer1-period interrupt tcint1 19 0028h y ev.gpt1 timer1-compare interrupt tufint1 20 0029h y ev.gpt1 timer1-underflow interrupt tofint1 21 002ah y ev.gpt1 timer1-overflow interrupt tpint2 22 002bh y ev.gpt2 timer2-period interrupt tcint2 23 int3 002ch y ev.gpt2 timer2-compare interrupt tufint2 24 int3 0006h 002dh y ev.gpt2 timer2-underflow interrupt tofint2 25 0006h evivrb 002eh y ev.gpt2 timer2-overflow interrupt tpint3 26 (event m (7433h) 002fh y ev.gpt3 timer3-period interrupt tcint3 27 m anager grou p b) 0030h y ev.gpt3 timer3-compare interrupt tufint3 28 grou b) 0031h y ev.gpt3 timer3-underflow interrupt tofint3 29 0032h y ev.gpt3 timer3-overflow interrupt capint1 30 int4 0033h y ev.cap1 capture 1 interrupt capint2 31 0008h evivrc 0034h y ev.cap2 capture 2 interrupt capint3 32 (event manager (7434h) 0035h y ev.cap3 capture 3 interrupt capint4 33 m anager group c) 0036h y ev.cap4 capture 4 interrupt
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 26 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) table 7. 'x240 interrupt locations and priorities (continued) interrupt name overall priority dsp-core interrupt, and address peripheral vector address peripheral vector address offset maskable? 'x240 source peripheral module function interrupt spiint 34 int5 sysivr 0005h y spi low-priority spi interrupt rxint 35 000ah sysivr (701eh) 0006h y sci sci receiver interrupt (low priority) txint 36 (system) 0007h y sci sci transmitter interrupt (low priority) adcint 37 int6 sysivr 0004h y adc analog-to-digital interrupt xint1 xint2 38 39 000ch (701eh) 0001h 0011h y y external low-priority external xint2 xint3 39 40 (system) (701eh) 0011h 001fh y y pins y user interrupts reserved 41 000eh n/a y dsp core used for analysis trap n/a 0022h n/a n/a trap instruction vector external interrupts the 'x240 has five external interrupts. these interrupts include: xint1. type a interrupt. the xint1 control register (at 7070h) provides control and status for this interrupt. xint1 can be used as a high-priority (level 1) or low-priority (level 6) maskable interrupt or as a general-purpose input pin. xint1 can also be programmed to trigger an interrupt on either the rising or the falling edge. nmi. type a interrupt. the nmi control register (at 7072h) provides control and status for this interrupt. nmi is a nonmaskable external interrupt or a general-purpose input pin. nmi can also be programmed to trigger an interrupt on either the rising or the falling edge. xint2. type c interrupt. the xint2 control register (at 7078h) provides control and status for this interrupt. xint2 can be used as a high-priority (level 1) or low-priority (level 6) maskable interrupt or a general-purpose i/o pin. xint2 can also be programmed to trigger an interrupt on either the rising or the falling edge. xint3. type c interrupt. the xint3 control register (at 707ah) provides control and status for this interrupt. xint3 can be used as a high-priority (level 1) or low-priority (level 6) maskable interrupt or as a general-purpose i/o pin. xint3 can also be programmed to trigger an interrupt on either the rising or the falling edge. pdpint. this interrupt is provided for safe operation of the power converter and motor drive. this maskable interrupt can put the timers and pwm output pins in the high-impedance state and inform the cpu in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. pdpint is a level 2 interrupt.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 27 post office box 1443 ? houston, texas 772511443 external interrupts (continued) table 8 is a summary of the external interrupt capability of the 'x240. table 8. external interrupt types and functions external interrupt control register name control register address interrupt type can do nmi? digital i/o pin maskable? xint1 xint1cr 7070h a no input only yes (level 1 or 6) nmi nmicr 7072h a yes input only no xint2 xint2cr 7078h c no i/o yes (level 1 or 6) xint3 xint3cr 707ah c no i/o yes (level 1 or 6) pdpint evimra 742ch n/a n/a n/a yes (level 2) clock generation the tms320x240 has an on-chip, pll-based clock module. this module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. the only external component necessary for this module is an external fundamental crystal, or oscillator. the pll-based clock module provides two basic modes of operation: oscillator mode and clock-in mode. oscillator mode this mode allows the use of a 4-, 6-, or 8-mhz external reference crystal to provide the time base to the device. the internal oscillator circuitry is initialized by software to select the desired cpuclk frequency, which can be the input clock frequency, the input clock frequency divided by 2 (default), or a clock frequency determined by the pll. clock-in mode this mode allows the internal crystal oscillator circuitry to be bypassed. the device clocks are generated from an external clock source input on the xtal1/clkin pin. the device can be configured by software to operate on the input clock frequency, the input clock frequency divided by 2, or a clock frequency determined by the pll. the 'x240 runs on two clock frequencies: the cpu clock (cpuclk) frequency, and the system clock (sysclk) frequency. the cpu, memories, external memory interface, and event manager run at the cpuclk frequency. all other peripherals run at the sysclk frequency. the cpuclk runs at 2x or 4x the frequency of the sysclk; for example, for 2x, cpuclk = 20 mhz and sysclk = 10 mhz. there is also a clock for the watchdog timer, wdclk. this clock has a nominal frequency of 16384 hz (214 hz) when xtal1/clkin is a power of two or a sum of two powers of two; for example, 4194304 hz (222 hz), 6291456 (222 + 221 hz), or 8388608 hz (223 hz). the clock module includes three external pins: 1. xtal1/clkin clock source/crystal input 2. xtal2 output to crystal 3. oscbyp oscillator bypass for the external pins, if oscbyp v ih , then the oscillator is enabled and if oscbyp v il , then the oscillator is bypassed and the device is in clock-in mode. in clock-in mode, an external ttl clock must be applied to the xtal1/clkin pin. the xtal2 pin can be left unconnected.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 28 post office box 1443 ? houston, texas 772511443 clock generation (continued) cpuclk synchronizing clock switch vco aclk wdclk sysclk clock mode bits (ckcr0.76) div 2 mux mux div 2 xtal osc pll 1-mhz clock prescaler sysclk prescaler div 2 or 4 prescale bit (ckcr0.0) phase detector feedback divider div 1, 2, 3, 4, 5, or 9 watchdog clock prescaler clock frequency and pll multiply bits (ckcr1.74) xtal2 xtal1/clkin oscbyp pll divide-by-2 bit (ckcr1.3) pll multiply ratio (ckcr1.20) figure 8. pll clock module block diagram
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 29 post office box 1443 ? houston, texas 772511443 low-power modes the tms320x240 has four low-power modes (idle 1, idle 2, pll power down, and oscillator power down). the low-power modes reduce the operating power by reducing or stopping the activity of various modules (by stopping their clocks). the two pllpm bits of the clock module control register, ckcr0, select which of the low-power modes the device enters when executing an idle instruction. reset or an unmasked interrupt from any source causes the device to exit from idle 1 low-power mode. a real-time interrupt from the watchdog timer module causes the device to exit from all low-power modes except oscillator power down. this is a wake-up interrupt. when enabled, reset or any of the four external interrupts (nmi, xint1, xint2, or xint3) causes the device to exit from any of the low-power modes (idle 1, idle 2, pll power down, and oscillator power down). the external interrupts are all wake-up interrupts. the maskable external interrupts (xint1, xint2, and xint3) must be enabled individually and globally to bring the device out of a low-power mode properly. it is, therefore, important to ensure that the desired low-power-mode exit path is enabled before entering a low-power mode. figure 9 shows the wake-up sequence from a power down. table 9 summarizes the low-power modes. watchdog timer and real-time interrupt module nmi xint1 xint2 xint3 external-interrupt logic reset logic reset signal wake-up signal to cpu wake-up signal system module figure 9. waking up the device from power down table 9. low-power modes low- power mode pllpm(x) bits in ckcr0[2:3] cpuclk status sysclk status wdclk status pll status osc status exit condition typical power run xx on on on on on 80 ma idle 1 00 off on on on on any interrupt or reset 50 ma idle 2 01 off off on on on wake-up interrupt or reset 7 ma pll power down 10 off off on off on wake-up interrupt or reset 1 ma osc power down 11 off off off off off wake-up interrupt or reset 400 a
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 30 post office box 1443 ? houston, texas 772511443 functional block diagram of the tms320x240 dsp cpu 32 16 data bus 16 oscale (07) d15d0 a15a0 16 16 16 32 32 accl(16) acch(16) c 32 calu(32) 32 32 mux iscale (016) 16 mux preg(32) multiplier treg0(16) mux 16 16 mux b1 (256 16) b2 (32 16) daram b0 (256 16) daram 7 lsb from ir mux dp(9) 9 9 mux 16 16 arau(16) 16 3 3 3 3 arb(3) arp(3) program bus 16 16 16 16 ar7(16) ar6(16) ar5(16) ar3(16) ar2(16) ar1(16) ar0(16) stack 8 16 pc mux nmi we w/r 16 clkin/x2 clkout1 x1 3 xint[13] mp/mc rs xf br ready strb r/w ps ds is control data bus program bus data bus ar4(16) 16 mux mux data/prog 16 pscale (6, 0, 1, 4) 16 data 32 16 16 16 16 16 flash eeprom/ rom mux mux npar par mstack program control (pctrl) memory map register imr (16) ifr (16) greg (16) 16 program bus notes: a. symbol descriptions appear in table 10. b. for clarity the data and program buses are shown as single buses although they include address and data bits.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 31 post office box 1443 ? houston, texas 772511443 table 10. legend for the 'f240 internal hardware functional block diagram symbol name description acc accumulator 32-bit register that stores the results and provides input for subsequent calu operations. also includes shift and rotate capabilities arau auxiliary register arithmetic unit an unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs aux regs auxiliary registers 07 these 16-bit registers are used as pointers to anywhere within the data space address range. they are operated upon by the arau and are selected by the auxiliary register pointer (arp). ar0 can also be used as an index value for ar updates of more than one and as a compare value to ar. br bus request signal br is asserted during access of the external global data memory space. ready is asserted to the device when the global data memory is available for the bus transaction. br can be used to extend the data memory address space by up to 32k words. c carry register carry output from calu. c is fed back into the calu for extended arithmetic operation. the c bit resides in status register 1 (st1), and can be tested in conditional instructions. c is also used in accumulator shifts and rotates. calu central arithmetic logic unit 32-bit-wide main arithmetic logic unit for the tms320c2xx core. the calu executes 32-bit operations in a single machine cycle. calu operates on data coming from iscale or pscale with data from acc, and provides status results to pctrl. daram dual access ram if the on-chip ram configuration control bit (cnf) is set to 0, the reconfigurable data dual-access ram (daram) block b0 is mapped to data space; otherwise, b0 is mapped to program space. blocks b1 and b2 are mapped to data memory space only, at addresses 030003ff and 0060007f, respectively. blocks 0 and 1 contain 256 words, while block 2 contains 32 words. dp data memory page pointer the 9-bit dp register is concatenated with the seven lsbs of an instruction word to form a direct memory address of 16 bits. dp can be modified by the lst and ldp instructions. greg global memory allocation register greg specifies the size of the global data memory space. imr interrupt mask register imr individually masks or enables the seven interrupts. ifr interrupt flag register the 7-bit ifr indicates that the tms320c2xx has latched an interrupt from one of the seven maskable interrupts. int# interrupt traps a total of 32 interrupts by way of hardware and/or software are available. iscale input data-scaling shifter 16 to 32-bit barrel left-shifter. iscale shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. mpy multiplier 16 16-bit multiplier to a 32-bit product. mpy executes multiplication in a single cycle. mpy operates either signed or unsigned 2s-complement arithmetic multiply. mstack micro stack mstack provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. mux multiplexer multiplexes buses to a common input npar next program address register npar holds the program address to be driven out on the pab on the next cycle. oscale output data-scaling shifter 16 to 32-bit barrel left-shifter. oscale shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data bus (dweb). par program address register par holds the address currently being driven on pab for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle. pc program counter pc increments the value from npar to provide sequential addresses for instruction-fetching and sequential data-transfer operations. pctrl program controller pctrl decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 32 post office box 1443 ? houston, texas 772511443 table 10. legend for the 'f240 internal hardware functional block diagram (continued) symbol name description preg product register 32-bit register holds results of 16 16 multiply. pscale product-scaling shifter 0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. the left-shift options are used to manage the additional sign bits resulting from the 2s-complement multiply. the right-shift option is used to scale down the number to manage overflow of product accumulation in the calu. pscale resides in the path from the 32-bit product shifter and from either the calu or the data-write data bus (dweb), and requires no cycle overhead. stack stack stack is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. the 'c20x stack is 16-bit wide and eight-level deep. treg temporary register 16-bit register holds one of the operands for the multiply operations. treg holds the dynamic shift count for the lact, addt, and subt instructions. treg holds the dynamic bit position for the bitt instruction.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 33 post office box 1443 ? houston, texas 772511443 'x240 dsp core cpu the tms320x240 devices use an advanced harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures e program and data e for full-speed execution. this multiple bus structure allows data and instructions to be read simultaneously. instructions support data transfers between program memory and data memory. this architecture permits coefficients that are stored in program memory to be read in ram, thereby eliminating the need for a separate coefficient that are rom. this, coupled with a four-deep pipeline, allows the 'x240 devices to execute most instructions in a single cycle. status and control registers two status registers, st0 and st1, contain the status of various conditions and modes. these registers can be stored into data memory and loaded from data memory, thereby allowing the status of the machine to be saved and restored for subroutines. the load status register (lst) instruction is used to write to st0 and st1. the store status register (sst) instruction is used to read from st0 and st1 e except for the intm bit, which is not affected by the lst instruction. the individual bits of these registers can be set or cleared when using the setc and clrc instructions. figure 10 shows the organization of status registers st0 and st1, indicating all status bits contained in each. several bits in the status registers are reserved and are read as logic 1s. table 11 lists status register field definitions. 15 131211109876543210 st0 arp ov ovm 1 intm dp 15 13121110987654321 0 st1 arb cnf tc sxm c 1 1 1 1 xf 1 1 pm figure 10. status and control register organization table 11. status register field definitions field function arb auxiliary register pointer buffer. when the arp is loaded into st0, the old arp value is copied to the arb except during an lst instruction. when the arb is loaded by way of an lst #1 instruction, the same value is also copied to the arp. arp auxiliary register (ar) pointer. arp selects the ar to be used in indirect addressing. when the arp is loaded, the old arp valu e is copied to the arb register. arp can be modified by memory-reference instructions when using indirect addressing, and by the larp, mar, and lst instructions. the arp is also loaded with the same value as arb when an lst #1 instruction is executed. c carry bit. c is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. otherwise, c is reset after an addition or set after a subtraction, except if the instruction is add or sub with a 16-bit shift . in these cases, the add can only set and the sub only reset the carry bit, but cannot affect it otherwise. the single bit shift and rota te instructions also affect c, as well as the setc, clrc, and lst #1 instructions. branch instructions have been provided to branc h on the status of c. c is set to 1 on a reset. cnf on-chip ram configuration control bit. if cnf is set to 0, the reconfigurable data dual-access ram blocks are mapped to data space; otherwise, they are mapped to program space. the cnf can be modified by the setc cnf, clrc cnf, and lst #1 instructions. rs sets the cnf to 0. dp data memory page pointer. the 9-bit dp register is concatenated with the seven lsbs of an instruction word to form a direct memory address of 16 bits. dp can be modified by the lst and ldp instructions. intm interrupt mode bit. when intm is set to 0, all unmasked interrupts are enabled. when set to 1, all maskable interrupts are disa bled. intm is set and reset by the setc intm and clrc intm instructions. rs and iack also set intm. intm has no effect on the unmaskable rs and nmi interrupts. note that intm is unaffected by the lst instruction. this bit is set to 1 by reset. it is also set to 1 when a maskable interrupt trap is taken. ov overflow flag bit. as a latched overflow signal, ov is set to 1 when overflow occurs in the arithmetic logic unit (alu). once a n overflow occurs, the ov remains set until a reset, bcnd/d on ov/nov, or lst instructions clear ov.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 34 post office box 1443 ? houston, texas 772511443 status and control registers (continued) table 11. status register field definitions (continued) field function ovm overflow mode bit. when ovm is set to 0, overflowed results overflow normally in the accumulator. when set to 1, the accumulato r is set to either its most positive or negative value upon encountering an overflow. the setc and clrc instructions set and rese t this bit, respectively. lst can also be used to modify the ovm. pm product shift mode. if these two bits are 00, the multiplier's 32-bit product is loaded into the alu with no shift. if pm = 01, the preg output is left-shifted one place and loaded into the alu, with the lsb zero-filled. if pm = 10, preg output is left-shifted by four bits and loaded into the alu, with the lsbs zero-filled. pm = 11 produces a right shift of six bits, sign-extended. note that t he preg contents remain unchanged. the shift takes place when transferring the contents of the preg to the alu. pm is loaded by the spm and lst #1 instructions. pm is cleared by rs . sxm sign-extension mode bit. sxm = 1 produces sign extension on data as it is passed into the accumulator through the scaling shift er. sxm = 0 suppresses sign extension. sxm does not affect the definitions of certain instructions; for example, the adds instructi on suppresses sign extension regardless of sxm. sxm is set by the setc sxm and reset by the clrc sxm instructions, and can be loaded by the lst #1. sxm is set to 1 by reset. tc test / control flag bit. tc is affected by the bit, bitt, cmpr, lst #1, and norm instructions. tc is set to a 1 if a bit tested b y bit or bitt is a 1, if a compare condition tested by cmpr exists between ar (arp) and ar0, if the exclusive-or function of the two msbs of the accumulator is true when tested by a norm instruction. the conditional branch, call, and return instructions can execute based on the condition of tc. xf xf pin status bit. xf indicates the state of the xf pin, a general-purpose output pin. xf is set by the setc xf and reset by th e clrc xf instructions. xf is set to 1 by reset. central processing unit the tms320x240 central processing unit (cpu) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (calu), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. this section describes the cpu components and their functions. the functional block diagram shows the components of the cpu. input scaling shifter the tms320x240 provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the calu. this shifter operates as part of the path of data coming from program or data space to the calu and requires no cycle overhead. it is used to align the 16-bit data coming from memory to the 32-bit calu. this is necessary for scaling arithmetic as well as aligning masks for logical operations. the scaling shifter produces a left shift of 0 to 16 on the input data. the lsbs of the output are filled with zeros; the msbs can either be filled with zeros or sign-extended, depending upon the value of the sxm bit (sign-extension mode) of status register st1. the shift count is specified by a constant embedded in the instruction word or by a value in treg. the shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. the treg base shift allows the scaling factor to be adaptable to the system's performance. multiplier the tms320x240 devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. all multiply instructions, except the mpyu (multiply unsigned) instruction, perform a signed multiply operation. that is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. two registers are associated with the multiplier: 16-bit temporary register (treg) that holds one of the operands for the multiplier 32-bit product register (preg) that holds the product four product shift modes (pm) are available at the preg output (pscale). these shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. the pm field of status register st1 specifies the pm shift mode, as shown in table 12.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 35 post office box 1443 ? houston, texas 772511443 multiplier (continued) table 12. pscale product shift modes pm shift description 00 no shift product feed to calu or data bus with no shift 01 left 1 removes the extra sign bit generated in a 2s-complement multiply to produce a q31 product 10 left 4 removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a q31 product when using the multiply by a 13-bit constant 11 right 6 scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow the product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (mpy instruction). a four-bit shift is used in conjunction with the mpy instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. finally, the output of preg can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. the lt (load treg) instruction normally loads treg to provide one operand (from the data bus), and the mpy (multiply) instruction provides the second operand (also from the data bus). a multiplication also can be performed with a 13-bit immediate operand when using the mpy instruction. then a product is obtained every two cycles. when the code is executing multiple multiplies and product sums, the cpu supports the pipelining of the treg load operations with calu operations using the previous product. the pipeline operations that run in parallel with loading the treg include: load acc with preg (ltp); add preg to acc (lta); add preg to acc and shift treg input data (dmov) to next address in data memory (ltd); and subtract preg from acc (lts). two multiply/accumulate instructions (mac and macd) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. the data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. this facilitates single-cycle multiply/accumulates when used with the repeat (rpt) instruction. in these instructions, the coefficient addresses are generated by program address generation (pagen) logic, while the data addresses are generated by data address generation (dagen) logic. this allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. the macd instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. the mpyu instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. the unsigned contents of treg are multiplied by the unsigned contents of the addressed data memory location, with the result placed in preg. this process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. the sqra (square/add) and sqrs (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. after the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (preg). the product from preg can be transferred to the calu or to data memory by way of the sph (store product high) and spl (store product low). note: the transfer of preg to either the calu or data bus passes through the pscale shifter, and therefore is affected by the product shift mode defined by pm. this is important when saving preg in an interrupt-service-routine context save as the pscale shift effects cannot be modeled in the restore operation. preg can be cleared by executing the mpy #0 instruction. the product register can be restored by loading the saved low half into treg and executing a mpy #1 instruction. the high half, then, is loaded using the lph instruction.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 36 post office box 1443 ? houston, texas 772511443 central arithmetic logic unit the tms320x240 central arithmetic logic unit (calu) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. this alu is referred to as central to differentiate it from a second alu used for indirect-address generation called the auxiliary register arithmetic unit (arau). once an operation is performed in the calu, the result is transferred to the accumulator (acc) where additional operations, such as shifting, can occur. data that is input to the calu can be scaled by iscale when coming from one of the data buses (drdb or prdb) or scaled by pscale when coming from the multiplier. the calu is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. in addition to the usual arithmetic instructions, the calu can perform boolean operations, facilitating the bit manipulation ability required for a high-speed controller. one input to the calu is always provided from the accumulator, and the other input can be provided from the product register (preg) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the acc). after the calu has performed the arithmetic or logical operation, the result is stored in the accumulator. the tms320x240 devices support floating-point operations for applications requiring a large dynamic range. the norm (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. the four bits of the treg define a variable shift through the scaling shifter for the lact/addt/subt (load/add to /subtract from accumulator with shift specified by treg) instructions. these instructions are useful in floating-point arithmetic where a number needs to be denormalized e that is, floating-point to fixed-point conversion. they are also useful in execution of an automatic gain control (agc) going into a filter. the bitt (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four lsbs of treg. the calu overflow saturation mode can be enabled/disabled by setting/resetting the ovm bit of st0. when the calu is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. the value of the accumulator at saturation is 07fffffffh (positive) or 080000000h (negative). if the ovm (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (logical operations cannot result in overflow.) the calu can execute a variety of branch instructions that depend on the status of the calu and the accumulator. these instructions can be executed conditionally based on any meaningful combination of these status bits. for overflow management, these conditions include the ov (branch on overflow) and eq (branch on accumulator equal to zero). in addition, the bacc (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). bit test instructions (bit and bitt), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory. the calu also has an associated carry bit that is set or reset depending on various operations within the device. the carry bit allows more efficient computation of extended-precision products and additions or subtractions. it also is useful in overflow management. the carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. it is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. the addc (add to accumulator with carry) and subb (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. the one exception to the operation of the carry bit is in the use of add with a shift count of 16 (add to high accumulator) and sub with a shift count of 16 (subtract from high accumulator) instructions. this case of the add instruction can set the carry bit only if a carry is generated, and this case of the sub instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 37 post office box 1443 ? houston, texas 772511443 central arithmetic logic unit (continued) two conditional operands, c and nc, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. the setc, clrc, and lst #1 instructions also can be used to load the carry bit. the carry bit is set to one on a hardware reset. accumulator the 32-bit accumulator is the registered output of the calu. it can be split into two 16-bit segments for storage in data memory. shifters at the output of the accumulator provide a left shift of 0 to 7 places. this shift is performed while the data is being transferred to the data bus for storage. the contents of the accumulator remain unchanged. when the post-scaling shifter is used on the high word of the accumulator (bits 1631), the msbs are lost and the lsbs are filled with bits shifted in from the low word (bits 015). when the post-scaling shifter is used on the low word, the lsbs are zero-filled. the sfl and sfr (in-place one-bit shift to the left/right) instructions and the rol and ror (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. the sxm bit affects the definition of the sfr (shift accumulator right) instruction. when sxm = 1, sfr performs an arithmetic right shift, maintaining the sign of the accumulator data. when sxm = 0, sfr performs a logical shift, shifting out the lsbs and shifting in a zero for the msb. the sfl (shift accumulator left) instruction is not affected by the sxm bit and behaves the same in both cases, shifting out the msb and shifting in a zero. repeat (rpt) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (arau) the 'x240 provides a register file containing eight auxiliary registers (ar0 ar7). the auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. these registers are referenced with a 3-bit auxiliary register pointer (arp) that is loaded with a value from 0 through 7, designating ar0 through ar7, respectively. the auxiliary registers and the arp can be loaded from data memory, the acc, the product register, or by an immediate operand defined in the instruction. the contents of these registers also can be stored in data memory or used as inputs to the calu. the auxiliary register file (ar0 ar7) is connected to the arau. the arau can autoindex the current auxiliary register while the data memory location is being addressed. indexing either by 1 or by the contents of the ar0 register can be performed. as a result, accessing tables of information does not require the calu for address manipulation; therefore, the calu is free for other operations in parallel. internal memory the tms320x240 devices are configured with the following memory modules: dual-access random-access memory (daram) flash eeprom ('f240) mask rom ('c240) dual-access ram (daram) there are 544 words 16 bits of daram on the 'x240 device. the 'x240 daram allows writes to and reads from the ram in the same cycle. the daram is configured in three blocks: block 0 (b0), block 1 (b1), and block 2 (b2). block 1 contains 256 words and block 2 contains 32 words, and both blocks are located only in data memory space. block 0 contains 256 words, and can be configured to reside in either data or program memory space. the setc cnf (configure b0 as data memory) and clrc cnf (configure b0 as program memory) instructions allow dynamic configuration of the memory maps through software. when using block 0 as program memory, instructions can be downloaded from external program memory into on-chip ram and then executed. when using on-chip ram, or high-speed external memory, the 'x240 runs at full speed with no wait states. the ability of the daram to allow two accesses to be performed in one cycle coupled with the parallel nature of the 'x240
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 38 post office box 1443 ? houston, texas 772511443 dual-access ram (daram) (continued) architecture enables the device to perform three concurrent memory accesses in any given machine cycle. externally, the ready line can be used to interface the 'x240 to slower, less expensive external memory. downloading programs from slow off-chip memory to on-chip ram can speed processing while cutting system costs. rom (tms320c240 only) the 'c240 device contains 16k words of mask-programmable rom located in program memory space. customers can arrange to have this rom programmed with contents unique to any particular application. the rom is enabled or disabled by the state of the mp/mc control input upon resetting the device. the rom occupies the lowest block of the program memory when enabled. when disabled, these addresses are located in the device's external program memory space. flash eeprom (tms320f240 only) flash eeprom provides an attractive alternative to masked program rom. like rom, flash is a nonvolatile memory type; however, it has the advantage of ain-targeto reprogrammability. the tms320f240 incorporates one 16k 16-bit flash eeprom module in program space. this type of memory expands the capabilities of the tms320f240 in the areas of prototyping, early field-testing, and single-chip applications. unlike most discrete flash memory, the 'f240 flash does not require a dedicated state machine, because the algorithms for programming and erasing the flash are executed by the dsp core. this enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. for production programming, the ieee standard 1149.1 (jtag) scan port provides easy access to the on-chip ram for downloading the algorithms and flash code. other key features of the flash include zero-wait-state access rate and single 5-v power supply. an erased bit in the tms320f240 flash is read as a logic 1, and a programmed bit is read as a logic 0. the flash requires a block-erase of the entire 16k module; however, any combination of bits can be programmed. the following four algorithms are required for flash operations: clear, erase, flash-write, and program. for an explanation of these algorithms and a complete description of the flash eeprom, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282), which is available during the 2nd quarter of 1998. flash serial loader the on-chip flash is shipped with a serial bootloader code programmed at the following addresses: 0x00000x00ffh. all other flash addresses are in an erased state. the serial bootloader can be used to program the on-chip flash memory with user's code. during the flash programming sequence, the on-chip data ram is used to load and execute the clear, erase, and program algorithms. see the tms320f240 serial bootloader application report (currently located at ftp://ftp.ti.com/pub/tms320bbs/c24xfiles/f240boot.pdf to understand on-chip flash programming using the serial bootloader code. look for further c2000 information using the dsp link at www.ti.com . flash control mode register the flash control mode register is located at i/o address ff0fh. this register offers two options: register access mode and array access mode. register access mode gives access to the four control registers in the memory space decoded for the flash module. these registers are used to control erasing, programming, and testing of the flash array. register access mode is enabled by activating an out command with dummy data. the out xxxx, ff0fh instruction makes the flash registers accessible for reads and/or writes. after executing out xxxx, ff0fh , the flash control registers are accessed in the memory space decoded for the flash module and the flash array cannot be accessed. the four registers are repeated every four address locations within the flash module's decoded range.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 39 post office box 1443 ? houston, texas 772511443 flash control mode register (continued) after completing all the necessary reads and/or writes to the control registers, an in xxxx, ff0fh instruction (with dummy data) is executed to place the flash array back in array access mode. after executing the in xxxx, ff0fh instruction, the flash array is accessed in the decoded space and the flash registers are not available. switching between the register access mode and the array access mode is done by issuing the in and out instructions. the memory content in these instructions (denoted by xxxx ) is not relevant. refer to the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282) for a detailed description of the flash programming algorithms. peripherals the integrated peripherals of the tms320x240 are described in the following subsections: external memory interface event manager (ev) dual analog-to-digital converter (adc) serial peripheral interface (spi) serial communications interface (sci) watchdog timer (wd) external memory interface the tms320x240 can address up to 64k words 16 bits of memory or registers in each of the program, data, and i/o spaces. on-chip memory, when enabled, removes some of this off-chip range. in data space, the high 32k words can be mapped dynamically as either local or global using the greg register. a data-memory access mapped as global asserts br low (with timing similar to the address bus). the cpu of the tms320x240 schedules a program fetch, data read, and data write on the same machine cycle. this is because, from on-chip memory, the cpu can execute all three of these operations in the same cycle. however, the external interface multiplexes the internal buses to one address and one data bus. the external interface sequences these operations to complete the data write first, then the data read, and finally the program read. the 'x240 supports a wide range of system interfacing requirements. program, data, and i/o address spaces provide interface to memory and i/o, maximizing system throughput. the full 16-bit address and data bus, along with the ps , ds , and is space-select signals allow addressing of 64k 16-bit words in program and i/o space. due to the on-chip peripherals, external data space is addressable to 32k 16-bit words. i/o design is simplified by having i/o treated the same way as memory. i/o devices are mapped into the i/o address space using the processor's external address and data buses in the same manner as memory-mapped devices. the 'x240 external parallel interface provides control signals to facilitate interfacing to the device. the r/w output signal is provided to indicate whether the current cycle is a read or a write. the strb output signal provides a timing reference for all external cycles. interface to memory and i/o devices of varying speeds is accomplished by using the ready input. when transactions are made with slower devices, the 'x240 processor waits until the other device completes its function and signals the processor by way of the ready input. once a ready indication is provided from the external device, execution continues. on the 'x240 device, the ready input must be driven (active high) to complete reads or writes to internal data i/o-memory-mapped registers and all external addresses.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 40 post office box 1443 ? houston, texas 772511443 external memory interface (continued) the bus request (br ) signal is used in conjunction with the other 'x240 interface signals to arbitrate external global-memory accesses. global memory is external data-memory space in which the br signal is asserted at the beginning of the access. when an external global-memory device receives the bus request, it responds by asserting the ready signal after the global-memory access is arbitrated and the global access is completed. the tms320x240 supports zero-wait-state reads on the external interface. however, to avoid bus conflicts, writes take two cycles. this allows the 'x240 to buffer the transition of the data bus from input to output (or output to input) by a half cycle. in most systems, tms320x240 ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes. wait states can be generated when accessing slower external resources. the wait states operate on machine-cycle boundaries and are initiated either by using the ready signal or using the software wait-state generator. ready can be used to generate any number of wait states. event-manager (ev) module the event-manager module includes general-purpose (gp) timers, full compare units, capture units, and quadrature-encoder pulse (qep) circuits. figure 11 shows the functions of the event manager. general-purpose (gp) timers there are three gp timers on the tms320x240. the gp timer x (for x = 1, 2, 3) includes: a 16-bit timer up-, up/down-counter, txcnt for reads or writes a 16-bit timer-compare register (double-buffered with shadow register), txcmpr for reads or writes a 16-bit timer-period register (double-buffered with shadow register), txpr for reads or writes a 16-bit timer-control register,txcon for reads or writes selectable internal or external input clocks a programmable prescalar for internal or external clock inputs control and interrupt logic for four maskable interrupts: underflow, overflow, timer compare, and period interrupts a timer-compare output pin with configurable active-low and active-high states, as well as forced-low and forced-high states. a selectable direction (tmrdir) input pin (to count up or down when directional up- / down-count mode is selected) the gp timers can be operated independently or synchronized with each other. a 32-bit gp timer also can be configured using gp timer 2 and 3. the compare register associated with each gp timer can be used for compare function and pwm-waveform generation. there are two single and three continuous modes of operation for each gp timer in up- or up / down-counting operations. internal or external input clocks with programmable prescaler is used for each gp timer. the state of each gp timer/compare output is configurable by the general-purpose timer-control register (gptcon). gp timers also provide the time base for the other event-manager submodules: gp timer 1 for all the compares and pwm circuits, gp timer 1 or 2 for the simple compares to generate additional compare or pwms, gp timer 2 or 3 for the capture units and the quadrature-pulse counting operations. double buffering of the period and compare registers allows programmable change of the timer (pwm) period and the compare/pwm pulse width as needed.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 41 post office box 1443 ? houston, texas 772511443 16 dsp core data bus addr bus ev control registers and control logic gp timer 1 compare full compare units gp timer 2 compare gp timer 2 mux simple compare units gp timer 3 compare mux capture units 16 16 16 16 16 16 gp timer 1 gp timer 3 3 int2, 3, 4 2 tmrclk tmrdir adc start t1pwm / t1cmp svpwm state machine dead band units output logic 33 pwm1 / cmp1 3 pwm6 / cmp6 output logic 3 t2pwm / t2cmp output logic 3 pwm8 / cmp8 pwm7 / cmp7 pwm9 / cmp9 output logic t3pwm / t3cmp 2 2 2 qep circuit to control logic clock dir cap1 / qep1 cap2 / qep2 cap3, 4 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 internal clock reset output logic figure 11. event-manager block diagram
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 42 post office box 1443 ? houston, texas 772511443 full compare units there are three full compare units on tms320x240. these compare units use gp timer1 as the timebase and generate six outputs for compare and pwm-waveform generation using programmable deadband circuit. the state of each of the six outputs is configured independently. the compare registers of the compare units are double-buffered, allowing programmable change of the compare/pwm pulse widths as needed. programmable-deadband generator the deadband generator circuit includes three 8-bit counters and an 8-bit compare register. desired deadband value (from 0 to 102 s) can be programmed into the compare register for the outputs of the three compare units. the deadband generation can be enabled/disabled for each compare unit output individually. the deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. the output states of the deadband generator are configurable and changeable as needed by way of the double-buffered actr register. simple compares tms320x240 is equipped with three simple compares that can be used to generate three additional independent compare or high-precision pwm waveforms. gp timer1 or 2 can be selected as the timebase for the three simple compares. the states of the outputs of the three simple compares are configurable as low-active, high-active, forced-low, or forced-high independently. simple compare registers are double-buffered, allowing programmable change of the compare/pwm pulse widths as needed. the state of the simple-compare outputs is configurable and changeable as needed by way of the double-buffered sactr register. compare/ pwm waveform generation up to 12 compare and/or pwm waveforms (outputs) can be generated simultaneously by tms320x240: three independent pairs (six outputs) by the three full compare units with programmable deadbands , three independent compares or pwms (three outputs) by the simple compares, and three independent compare and pwms (three outputs) by the gp-timer compares. compare/pwms characteristics characteristics of the compare / pwms are as follow: 16-bit, 50-ns resolutions programmable deadband for the pwm output pairs, from 0 to 102 s minimum deadband width of 50 ns change of the pwm carrier frequency for pwm frequency wobbling as needed change of the pwm pulse widths within and after each pwm period as needed external maskable power and drive-protection interrupts pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector pwm waveforms minimized cpu overhead using auto-reload of the compare and period registers capture unit the capture unit provides a logging function for different events or transitions. the values of the gp timer 2 counter and/or gp timer 3 counter are captured and stored in the two-level first-in first-out (fifo) stacks when selected transitions are detected on capture input pins, capx for x = 1, 2, 3, or 4. the capture unit of the tms320x240 consists of four capture circuits.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 43 post office box 1443 ? houston, texas 772511443 capture unit (continued) the capture unit includes the following features: one 16-bit capture-control register, capcon, for reads or writes one 16-bit capture-fifo status register, capfifo, with eight msbs for read-only operations, and eight lsbs for write-only operations optional selection of gp timer 2 and/or gp timer 3 through two 16-bit multiplexers (muxs). one mux selects a gp timer for capture circuits 3 and 4, and the other mux selects a gp timer for capture circuits 1 and 2. four 16 bit x 2 fifo stack registers, one two-level fifo stack register per capture circuit. the top register of each stack is a read-only register, fifox, where x = 1, 2, 3, or 4. four possible schmitt-triggered capture-input pins (capx, x = 1 to 4) with one input pin per capture unit the input pins cap1 and cap2 also can be used as inputs to the qep circuit. user-specified edge-detection mode at the input pins four maskable interrupts/flags, capintx, where x = 1, 2, 3, or 4 quadrature-encoder pulse (qep) circuit two capture inputs (cap1 and cap2) can be used to interface the on-chip qep circuit with a quadrature encoder pulse. full synchronization of these inputs is performed on-chip. direction or leading-quadrature pulse sequence is detected, and gp timer 2 or 3 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). analog-to-digital converter (adc) module a simplified functional block diagram of the adc module is shown in figure 12. the adc module consists of two 10-bit adcs with two built-in sample-and-hold (s / h) circuits. a total of 16 analog input channels is available on the tms320x240. eight analog inputs are provided for each adc unit by way of an 8-to-1 analog multiplexer. minimum total conversion time for each adc unit is 6.1 s. total accuracy for each converter is 1.5 lsb. reference voltage for the adc module needs to be supplied externally through the two reference pins, v refhi and v reflo. the digital result is expressed as: digital result = 1023 x input voltage v refhi v reflo functions of the adc module include: two input channels (one for each adc unit) that can be sampled and converted simultaneously each adc unit can perform single or continuous s/h and conversion operations. two 2-level-deep fifo result registers for adc units 1 and 2 adc module (both a/d converters) can start operation by software instruction, external signal transition on a device pin, or by event-manager events on each of the gp timer/compare output and the capture 4 pins. the adc control register is double-buffered (with shadow register) and can be written to at any time. a new conversion of adc can start immediately or when the previous conversion process is completed according to the control register bits. at the end of each conversion, an interrupt flag is set and an interrupt is generated if it is unmasked/enabled.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 44 post office box 1443 ? houston, texas 772511443 analog-to-digital converter (adc) module (continued) control register (1) control register (2) control register sample- and- hold (s/h) circuit 8/1 mux adc 2 adc 3 adc 4 adc 5 adc 6 adc 7 control logic single/continues/event operations v cca v ref v ref v ssa v refhi v reflo supply voltage interrupts sleep mode adc 15 adc 14 adc 13 adc 12 adc 11 adc 10 external (i/o) start pin internal (ev module) start signal 10-bit a/d converter converter a/d 10-bit program clock prescaler internal bus sample- and- hold (s/h) circuit 8/1 mux adc0/io adc1/io adc8/io adc9/io figure 12. analog-to-digital converter module
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 45 post office box 1443 ? houston, texas 772511443 serial peripheral interface (spi) module the tms320x240 devices include the four-pin serial peripheral interface (spi) module. the spi is a high-speed synchronous serial-i/o port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multidevice communications are supported by the master/slave operation of the spi. the spi module features include the following: four external pins: spisomi: spi slave-output/master-input pin, or general-purpose bidirectional i/o pin spisimo: spi slave-input/master-output pin, or general-purpose bidirectional i/o pin spiste: spi slave-transmit-enable pin, or general-purpose bidirectional i/o pin spiclk: spi serial-clock pin, or general-purpose bidirectional i/o pin two operational modes: master and slave baud rate: 125 different programmable rates / 2.5 mbps at 10-mhz sysclk data word format: one to eight data bits four clocking schemes controlled by clock polarity and clock-phase bits include: falling edge without phase delay: spiclk active high. spi transmits data on the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. falling edge with phase delay: spiclk active high. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the falling edge of the spiclk signal. rising edge without phase delay: spiclk inactive low. spi transmits data on the rising edge of the spiclk signal and receives data on the falling edge of the spiclk signal. rising edge with phase delay: spiclk inactive low. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. simultaneous receive and transmit operations (transmit function can be disabled in software) transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. ten spi module control registers: located in control register frame beginning at address 7040h. note: all registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. when a register is acces sed, the register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. writing to the upper byte has no effect. figure 13 is a block diagram of the spi in slave mode.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 46 post office box 1443 ? houston, texas 772511443 serial peripheral interface (spi) module (continued) s s spipc1.3 0 clock polarity talk sysclk 4 5 6 0 1 2 spi bit rate state control spibuf buffer register 8 clock phase 1 2 30 receiver overrun spictl.4 overrun int ena spiccr.2 0 spibrr.6 0 spiccr.6 spictl.3 spibuf.7 0 spidat.7 0 spictl.1 m s m master/slave 2 spi int flag spictl.0 spi int ena spipc2.7 4 spipc2.3 0 spists.7 spidat data register spists.6 m s spipc1.5 spictl.2 spi char external connections spisimo spisomi spipc1.7 4 spiste spiclk sw2 s m m s sw3 to cpu spiste function 3 m sw1 spipri.6 spi priority level 1 int 1 0 level 6 int 2 the diagram is shown in the slave mode. 3 the spiste pin is shown as being disabled, meaning that data cannot be transmitted in this mode. note that sw1, sw2, and sw3 ar e closed in this configuration. figure 13. four-pin serial peripheral interface module block diagram 2
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 47 post office box 1443 ? houston, texas 772511443 serial communications interface (sci) module the tms320x240 devices include a serial communications interface (sci) module. the sci module supports digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the sci receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. to ensure data integrity, the sci checks received data for break detection, parity, overrun, and framing errors. the bit rate (baud) is programmable to over 65 000 different speeds through a 16-bit baud-select register. features of the sci module include: two external pins scitxd: sci transmit-output pin or general-purpose bidirectional i/o pin scirxd: sci receive-input pin or general-purpose bidirectional i/o pin baud rate programmable to 64k different rates up to 625 kbps at 10-mhz sysclk data word format one start bit data word length programmable from one to eight bits optional even/odd/no parity bit one or two stop bits four error-detection flags: parity, overrun, framing, and break detection two wake-up multiprocessor modes: idle-line and address bit half- or full-duplex operation double-buffered receive and transmit functions transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. transmitter: txrdy flag (transmitter-buffer register is ready to receive another character) and tx empty flag (transmitter-shift register is empty) receiver: rxrdy flag (receiver-buffer register is ready to receive another character), brkdt flag (break condition occurred), and rx error (monitoring four interrupt conditions) separate enable bits for transmitter and receiver interrupts (except brkdt) nrz (non return-to-zero) format eleven sci module control registers located in the control register frame beginning at address 7050h note: all registers in this module are 8-bit registers that are interfaced to the 16-bit peripheral bus. when a register is acce ssed, the register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. writing to the upper byte has no effect. figure 14 shows the sci module block diagram.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 48 post office box 1443 ? houston, texas 772511443 serial communications interface (sci) module (continued) sysclk wut frame format and mode even/odd enable parity sci rx interrupt brkdt scictl1.1 rxrdy scirxst.6 scictl1.3 external connections 8 scictl2.1 rx/bk int ena scirxd scirxst.1 txena sci tx interrupt tx empty txrdy scictl2.0 tx int ena scipc2.74 scitxd rxena scipc2.30 scirxd clock ena scictl1.4 rxwake scictl1.0 scictl1.6 rx err int ena txwake scitxd txint sciccr.6 sciccr.5 scitxbuf.70 scihbaud. 15 8 baud rate register (msbyte) scilbaud. 7 0 scirxbuf.70 receiver-data buffer register scirxst.7 pe fe oe rx error rx error scirxst.4 2 transmitter-data buffer register 8 scictl2.6 scictl2.7 baud rate register (lsbyte) rxshf register txshf register scirxst.5 rxint 1 scipri.5 scipri.6 sci priority level level 2 int. level 1 int. level 2 int. level 1 int. 1 0 1 0 sci tx priority sci rx priority figure 14. serial communications interface (sci) module block diagram
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 49 post office box 1443 ? houston, texas 772511443 watchdog (wd) and real-time interrupt (rti) module the tms320c240 device includes a watchdog (wd) timer and a real-time interrupt (rti) module. the wd function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. the rti function provides interrupts at programmable intervals. see figure 15 for a block diagram of the wd / rti module. the wd/rti module features include the following: wd timer seven different wd overflow rates ranging from 15.63 ms to 1 s a wd-reset key (wdkey) register that clears the wd counter when a correct value is written, and generates a system reset if an incorrect value is written to the register a wd flag (wd flag) that indicates whether the wd timer initiated a system reset wd check bits that initiate a system reset if an incorrect value is written to the wd control register (wdcr) automatic activation of the wd timer, once system reset is released three wd control registers located in control register frame beginning at address 7020h. real-time interrupt (rti): interrupt generation at a programmable frequency of 1 to 4 096 interrupts per second interrupt or polled operation two rti control registers located in control register frame beginning at address 7020h. note: all registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. when a register is acces sed, the register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. writing to the upper byte has no effect. figure 15 shows the wd/rti block diagram.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 50 post office box 1443 ? houston, texas 772511443 watchdog (wd) and real-time interrupt (rti) module (continued) 55 + aa detector d clr system reset request wdcntr.7 0 q int request (level 1 only) /16384 /2048 /512 /256 111 110 101 100 011 010 000 001 clr 8-bit real-time counter 7-bit free- running counter /128 /64 /32 /16 /8 /4 /2 111 110 101 100 011 010 001 000 any write 16-khz wdclk system reset system reset clr clr one-cycle delay watchdog reset key register 8-bit watchdog counter clr rticntr.7 0 d clr q int acknowledge bad wdcr key good key bad key wdps wdcr.2 0 210 wdkey.7 0 wdchk20 wdcr.5 3 2 wdcr.7 wd flag reset flag rtips rticr.2 0 210 rticr.7 rti flag clear rti flag rticr.7 rti flag read rti flag rticr.7 rti flag clear rti flag rticr.6 rti ena ps/257 wddis wdcr.6 101 (constant value) 3 3 2 writing to bits wdcr.5 3 with anything but the correct pattern (101) generates a system reset. figure 15. wd / rti module block diagram
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 51 post office box 1443 ? houston, texas 772511443 scan-based emulation tms320x240 devices use scan-based emulation for code- and hardware-development support. serial scan interface is provided by the test-access port. scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. tms320x240 instruction set the 'x240 microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. source code for the 'c1x and 'c2x dsps is upwardly compatible with the 'x2xx devices. for maximum throughput, the next instruction is prefetched while the current one is being executed. because the same data lines are used to communicate to external data, program, or i/o space, the number of cycles an instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or external memory. highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes the tms320x240 instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. in direct addressing, the instruction word contains the lower seven bits of the data memory address. this field is concatenated with the nine bits of the data memory page pointer (dp) to form the 16-bit data memory address. therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, each page containing 128 words. indirect addressing accesses data memory through the auxiliary registers. in this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. eight auxiliary registers (ar0 ar7) provide flexible and powerful indirect addressing. to select a specific auxiliary register, the auxiliary register pointer (arp) is loaded with a value from 0 to 7 for ar0 through ar7, respectively. there are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or subtracting the contents of ar0, single-indirect addressing with no increment or decrement, and bit-reversed addressing [used in fast fourier transforms (ffts)] with increment or decrement. all operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and arp can be modified. in immediate addressing, the actual operand data is provided in a portion of the instruction word or words. there are two types of immediate addressing: long and short. in short-immediate addressing, the data is contained in a portion of the bits in a single-word instruction. in long-immediate addressing, the data is contained in the second word of a two-word instruction. the immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution (for example, initialization values or constants). the register-addressing mode uses operands in cpu registers either explicitly, such as with a direct reference to a specific register, or implicitly, with instructions that intrinsically reference certain registers. in either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. repeat feature the repeat function can be used with instructions (as defined in table 14) such as multiply/accumulates (mac and macd), block moves (bldd and blpd), i/o transfers (in/out ), and table read/writes (tblr/tblw). these instructions, although normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. for example, the table-read instruction can take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 52 post office box 1443 ? houston, texas 772511443 repeat feature (continued) the repeat counter (rptc) is loaded with the addressed data-memory location if direct or indirect addressing is used, and with an 8-bit immediate value if short-immediate addressing is used. the rptc register is loaded by the rpt instruction. this results in a maximum of n + 1 executions of a given instruction. rptc is cleared by reset. once a repeat instruction (rpt ) is decoded, all interrupts, including nmi (but excluding reset), are masked until the completion of the repeat loop. instruction set summary this section summarizes the operation codes (opcodes) of the instruction set for the 'x240 digital signal processors. this instruction set is a superset of the 'c1x and 'c2x instruction sets. the instructions are arranged according to function and are alphabetized by mnemonic within each category. the symbols in table 13 are used in the instruction set summary table (table 14). t he ti 'c2xx assembler accepts 'c2x instructions. the number of words that an instruction occupies in program memory is specified in column 3 of table 14. several instructions specify two values separated by a slash mark ( / ) for the number of words. in these cases, different forms of the instruction occupy a different number of words. for example, the add instruction occupies one word when the operand is a short-immediate value or two words if the operand is a long-immediate value. the number of cycles that an instruction requires to execute is also in column 3 of table 14. all instructions are assumed to be executed from internal program memory (ram) and internal data dual-access memory. the cycle timings are for single-instruction execution, not for repeat mode.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 53 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 13. tms320x240 opcode symbols symbol description a address acc accumulator accb accumulator buffer arx auxiliary register value (0 7) bitx 4-bit field that specifies which bit to test for the bit instruction bmar block-move address register dbmr dynamic bit-manipulation register i addressing-mode bit ii...ii immediate operand value intm interrupt-mode flag bit intr# interrupt vector number k constant preg product register prog program memory rptc repeat counter shf, shft 3/4-bit shift value tc test-control bit t p two bits used by the conditional execution instructions to represent the conditions tc, ntc, and bio. t p meaning 0 0 bio low 0 1 tc = 1 1 0 tc = 0 1 1 none of the above conditions tregn temporary register n (n = 0, 1, or 2) z l v c 4-bit field representing the following conditions: z: acc = 0 l: acc < 0 v: overflow c: carry a conditional instruction contains two of these 4-bit fields. the 4-lsb field of the instruction is a 4-bit mask field. a 1 in the corresponding mask bit indicates that the condition is being tested. the second 4-bit field (bits 4 7) indicates the state of the conditions designated by the mask bits as being tested. for example, to test for acc 0, the z and l fields are set while the v and c fields are not set. the next 4-bit field contains the state of the conditions to test. the z field is set to indica te testing of the condition acc = 0, and the l field is reset to indicate testing of the condition acc 0. the conditions possible with these 8 bits are shown in the bcnd and cc instructions. to determine if the conditions are met, the 4-lsb bit mask is anded with the conditions. if any bits are set, the conditions are met.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 54 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 14. tms320x240 instruction set summary 'x240 description words/ opcode mnemonic description cycles msb lsb abs absolute value of accumulator 1/1 1011 1110 0000 0000 add to accumulator with shift 1/1 0010 shft iadd ress add add to high accumulator 1/1 0110 0001 iadd ress add add to accumulator short immediate 1/1 1011 1000 kkkk kkkk add to accumulator long immediate with shift 2/2 1011 1111 1001 shft addc add to accumulator with carry 1/1 0110 0000 iadd ress adds add to low accumulator with sign extension suppressed 1/1 0110 0010 iadd ress addt add to accumulator with shift specified by t register 1/1 0110 0011 iadd ress adrk add to auxiliary register short immediate 1/1 0111 1000 kkkk kkkk and with accumulator 1/1 0110 1110 iadd ress and immediate with accumulator with shift 2/2 1011 1111 1011 shft and and immediate with accumulator with shift 2/2 16-bit constant and immediate with accumulator with shift of 16 2/2 1011 1110 1000 0001 and immediate with accumulator with shift of 16 2/2 16-bit constant apac add p register to accumulator 1/1 1011 1110 0000 0100 b branch unconditionally 2/4 0111 1001 iadd ress b branch unconditionally 2/4 branch address bacc branch to address specified by accumulator 1/4 1011 1110 0010 0000 banz branch on auxiliary register not zero 2/4/2 0111 1011 iadd ress banz branch on auxiliary register not zero 2/4/2 branch address branch if tc bit 0 2/4/2 1110 0001 0000 0000 branch if tc bit ??? ?????? ??????? ?????? ?? ?? ?? ??? ??? ? ?????? ?? ?? ?? ??? ?????? ??????? ?????? ?? ???? ??? ??? ?? ? ? ?????? ?? ???? ??? ?????? ??????? ?????? ?? ????????? 0 2/4/2 1110 0011 1000 1100 branch if accumulator ??? ?????? ??????? ?????? ?? ????????? > 0 2/4/2 1110 0011 0000 0100 branch if accumulator > 0 2/4/2 branch address bcnd branch on i/o status low 2/4/3 1110 0000 0000 0000 branch on i/o status low 2/4/3 branch address branch if accumulator 0 2/4/2 1110 0011 1100 1100 branch if accumulator ??? ?????? ??????? ?????? ?? ????????? < 0 2/4/2 1110 0011 0100 0100 branch if acc u m u lator < 0 2/4/2 branch address branch on no carry 2/4/2 1110 0011 0000 0001 branch on no carr y 2/4/2 branch address branch if no overflow 2/4/2 1110 0011 0000 0010 branch if no o v erflo w 2/4/2 branch address
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 55 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 14. tms320x240 instruction set summary (continued) 'x240 description words/ opcode mnemonic description cycles msb lsb branch if accumulator 0 2/4/2 1110 0011 0000 1000 branch if acc u m u lator ??? ?????? ??????? ???? ?????? ?? ???????? ??? ??? ?? ? ? ???? ?????? ?? ? ? ????? ? ??? ?????? ??????? ?????? ?? ????????? ??? ??? ?? ? ? ?????? ?? ??? ????? ??? ?????? ??????? ??? ???? ?? ?? ? ??? ???? ??? ???? ???? ?? ???????? ? ??? ?? ?? ???? ???? ??? 2 ????? ??? ??? ???? ??? ?? ???? ??? ????? ???????? ?? ?? ? ???? ??? ???? 2 ????? ? ? ? ??? ???? ??? ?? ???? ??? ?? ??? ???????? ?? ?????? ??????? ???? 2 ????? ??? ??? ???? ??? ?? ???? ??? ??????????? ???????? ?? ?? ?? ???? ??? ????? ? ? ? ??? ???? ??? ?? ???? ??? ??????????? ???????? ?? ?????? ??????? ??? ????? ??? ??? ????? ??? ?? ???? ??? ?? ?? ?? ???? ??? ??? ????? ? ? ? ??? ????? ??? ?? ???? ??? ?? ?????? ??????? ???? ???? ??????? ???????? ?? ??? ??? ?? ???? ???? ??????? ?? ??? ?? ???? ??? ???? ???? ? ?? ???? ?? ????? ??????? ?? ??????????? ???? ??????? ??? ??? ?? ???? ???? ?? ??????????? ???? ? ?? ???? ??? ????? ??????? ???????? ???? ?? ???? ??? ?? ??? ??? ? ? ????? ??????? ?? ??? ??? ? ???? ???? ?? ?? ??? ??? ? ??? ??? ???? ???????? ??? ?? ??? ??? ? ? ???? ???????????? ??? ?? ??? ??? ? ?? ???? ???? ??????? ???? ?? ??? ??? ? ?? ???? ??????? ???? ?? ??? ??? ? ?? ??? ???????? ????????? ?? ??? ??? ? ??? ?????? ?????? ???????? ???? ?????? ???????? ?? ?? ??? ???? ? ??? ??? ???? ??? ?? ???? ??? ?? ??? ??? ???? ??? ???? ???? ???? ??????? ?? ??? ??? ? ? ?? ?? ? ???? ??? ??? ?? ?? ???? ???? ??? ?? ?? ? ???? ??? ??? ?? ?M??? ?? ?? ??? ??? ??????????????? ?? ??? ??? ??k kkkk ???? ????????? ???? ????? ?? ? ???? ???? ??? ???? ???? ????????? ???? ???????? ???? ????? ?? ??? ???? ? ???? ???? ???? ??? ????? ???? ???????? ? ??? ????? ?? ?M??? ???????? ???? ??? ????????? ??? ???? ???? ????????? ?? ?? ?? ???? ??? 2 ?? ??? ??????? ??? ???? ?????????? ???? ??? ???? ???? ???????? ????????? ??? ??? ??? ???
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 56 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 14. tms320x240 instruction set summary (continued) 'x240 description words/ opcode mnemonic description cycles msb lsb load accumulator immediate short 1/1 1011 1001 kkkk kkkk lacl zero accumulator 1/1 1011 1001 0000 0000 lacl zero low accumulator and load high accumulator 1/1 0110 1010 iadd ress zero low accumulator and load low accumulator with no sign extension 1/1 0110 1001 iadd ress lact load accumulator with shift specified by t register 1/1 0110 1011 iadd ress load auxiliary register 1/2 0000 0arx iadd ress lar load auxiliary register short immediate 1/2 1011 0arx kkkk kkkk lar load auxiliary register long immediate 2/2 1011 1111 0000 1arx load a ux iliar y register long immediate 2/2 16-bit constant ldp load data-memory page pointer 1/2 0000 1101 iadd ress ldp load data-memory page pointer immediate 1/2 1011 110p agep oint lph load high-p register 1/1 0111 0101 iadd ress lst load status register st0 1/2 0000 1110 iadd ress lst load status register st1 1/2 0000 1111 iadd ress lt load treg 1/1 0111 0011 iadd ress lta load treg and accumulate previous product 1/1 0111 0000 iadd ress ltd load treg, accumulate previous product, and move data 1/1 0111 0010 iadd ress ltp load treg and store p register in accumulator 1/1 0111 0001 iadd ress lts load treg and subtract previous product 1/1 0111 0100 iadd ress mac multi p ly and accumulate 2/3 1010 0010 iadd ress mac m u ltipl y and acc u m u late 2/3 16-bit constant macd multi p ly and accumulate with data move 2/3 1010 0011 iadd ress macd m u ltipl y and acc u m u late w ith data mo v e 2/3 16-bit constant mar load auxiliary register pointer 1/1 1000 1011 1000 1arx mar modify auxiliary register 1/1 1000 1011 iadd ress mpy multiply (with treg, store product in p register) 1/1 0101 0100 iadd ress mpy multiply immediate 1/1 110c kkkk kkkk kkkk mpya multiply and accumulate previous product 1/1 0101 0000 iadd ress mpys multiply and subtract previous product 1/1 0101 0001 iadd ress mpyu multiply unsigned 1/1 0101 0101 iadd ress neg negate accumulator 1/1 1011 1110 0000 0010 nmi nonmaskable interrupt 1/4 1011 1110 0101 0010 nop no operation 1/1 1000 1011 0000 0000 norm normalize contents of accumulator 1/1 1010 0000 iadd ress or with accumulator 1/1 0110 1101 iadd ress or immediate with accumulator with shift 2/2 1011 1111 1100 shft or or immediate w ith acc u m u lator w ith shift 2/2 16-bit constant or immediate with accumulator with shift of 16 2/2 1011 1110 1000 0010 or immediate w ith acc u m u lator w ith shift of 16 2/2 16-bit constant out output data to port 2/3 0000 16bit 1100 i/o iadd port ress adrs pac load accumulator with p register 1/1 1011 1110 0000 0011
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 57 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 14. tms320x240 instruction set summary (continued) 'x240 description words/ opcode mnemonic description cycles msb lsb pop pop top of stack to low accumulator 1/1 1011 1110 0011 0010 popd pop top of stack to data memory 1/1 1000 1010 iadd ress pshd push data-memory value onto stack 1/1 0111 0110 iadd ress push push low accumulator onto stack 1/1 1011 1110 0011 1100 ret return from subroutine 1/4 1110 1111 0000 0000 retc conditional return from subroutine 1/4/2 1110 11tp zlvc zlvc rol rotate accumulator left 1/1 1011 1110 0000 1100 ror rotate accumulator right 1/1 1011 1110 0000 1101 rpt repeat instruction as specified by data-memory value 1/1 0000 1011 iadd ress rpt repeat instruction as specified by immediate value 1/1 1011 1011 kkkk kkkk sach store high accumulator with shift 1/1 1001 1shf iadd ress sacl store low accumulator with shift 1/1 1001 0shf iadd ress sar store auxiliary register 1/1 1000 0arx iadd ress sbrk subtract from auxiliary register short immediate 1/1 0111 1100 kkkk kkkk set carry bit 1/1 1011 1110 0100 1111 configure block as program memory 1/1 1011 1110 0100 0101 disable interrupt 1/1 1011 1110 0100 0001 setc set overflow mode 1/1 1011 1110 0100 0011 set test / control flag 1/1 1011 1110 0100 1011 set external flag xf 1/1 1011 1110 0100 1101 set sign-extension mode 1/1 1011 1110 0100 0111 sfl shift accumulator left 1/1 1011 1110 0000 1001 sfr shift accumulator right 1/1 1011 1110 0000 1010 spac subtract p register from accumulator 1/1 1011 1110 0000 0101 sph store high-p register 1/1 1000 1101 iadd ress spl store low-p register 1/1 1000 1100 iadd ress spm set p register output shift mode 1/1 1011 1111 iadd ress sqra square and accumulate 1/1 0101 0010 iadd ress sqrs square and subtract previous product from accumulator 1/1 0101 0011 iadd ress sst store status register st0 1/1 1000 1110 iadd ress sst store status register st1 1/1 1000 1111 iadd ress splk store long immediate to data memory 2/2 1010 1110 iadd ress splk store long immediate to data memor y 2/2 16-bit constant subtract from accumulator long immediate with shift 2/2 1011 1111 1010 shft s u btract from acc u m u lator long immediate w ith shift 2/2 16-bit constant sub subtract from accumulator with shift 1/1 0011 shft iadd ress subtract from high accumulator 1/1 0110 0101 iadd ress subtract from accumulator short immediate 1/1 1011 1010 kkkk kkkk
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 58 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 14. tms320x240 instruction set summary (continued) 'x240 description words/ opcode mnemonic description cycles msb lsb subb subtract from accumulator with borrow 1/1 0110 0100 iadd ress subc conditional subtract 1/1 0000 1010 iadd ress subs subtract from low accumulator with sign extension suppressed 1/1 0110 0110 iadd ress subt subtract from accumulator with shift specified by treg 1/1 0110 0111 iadd ress tblr table read 1/3 1010 0110 iadd ress tblw table write 1/3 1010 0111 iadd ress trap software interrupt 1/4 1011 1110 0101 0001 exclusive-or with accumulator 1/1 0110 1100 iadd ress exclusive or immediate with accumulator with shift 2/2 1011 1111 1101 shft xor e x cl u si v e - or immediate w ith acc u m u lator w ith shift 2/2 16-bit constant exclusive or immediate with accumulator with shift of 16 2/2 1011 1110 1000 0011 e x cl u si v e - or immediate w ith acc u m u lator w ith shift of 16 2/2 16-bit constant zalr zero low accumulator and load high accumulator with rounding 1/1 0110 1000 iadd ress development support texas instruments offers an extensive line of development tools for the 'x240 generation of dsps, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of 'x240-based applications: software development tools: assembler/linker simulator optimizing ansi c compiler application algorithms c/assembly debugger and code profiler hardware development tools: emulator xds510 (supports 'x240 multiprocessor system debug) the tms320 family development support reference guide (literature number spru011) contains information about development-support products for all tms320 family member devices, including documentation. refer to this document for further information about tms320 documentation or any other tms320 support products from texas instruments. an additional document, the tms320 third party support reference guide (literature number spru052), contains information about tms320-related products from other companies in the industry. to receive copies of tms320 literature, contact the literature response center at 800/477-8924. see table 15 and table 16 for complete listings of development-support tools for the 'x240. for information on pricing and availability, contact the nearest ti field sales office or authorized distributor.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 59 post office box 1443 ? houston, texas 772511443 development support (continued) table 15. development support tools development tool platform part number software compiler/assembler/linker sparc ? tmds3242555-08 compiler/assembler/linker pc-dos ? tmds3242855-02 assembler/linker pc-dos, os/2 ? tmds3242850-02 'c2xx simulator pc-dos, win ? tmdx324x851-02 'c2xx simulator sparc tmdx324x551-09 digital filter design package pc-dos dfdp 'c2xx debugger/emulation software pc-dos, os/2, win tmdx324012xx 'c2xx debugger/emulation software sparc tmdx324062xx hardware xds510 xl emulator pc-dos, os/2 tmds00510 xds510 ws emulator sparc tmds00510ws table 16. tms320x240-specific development tools development tool platform part number hardware c24x evm pc tmdx326p124x device and development-support tool nomenclature to designate the stages in the product development cycle, texas instruments assigns prefixes to the part numbers of all tms320 devices and support tools. each tms320 member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). this development flow is defined below. device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development support product that has not completed ti's internal qualification testing tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: adevelopmental product is intended for internal evaluation purposes.o sparc is a trademark of sparc international, inc. pc-dos and os/2 are trademarks of international business machines corp. win is a trademark of microsoft corp.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 60 post office box 1443 ? houston, texas 772511443 device and development-support tool nomenclature (continued) tms devices and tmds development-support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. ti's standard warranty applies. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate is still undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pn, pq, and pz) and temperature range (for example, l). figure 16 provides a legend for reading the complete device name for any tms320x2xx family member. prefix temperature range (default: 0 c to 70 c) tms 320 c 240 pq (l) tmx = experimental device tmp = prototype device tms = qualified device device family 320 = tms320 family technology l=0 c to 70 c a=40 c to 85 c s=40 c to 125 c q= 40 c to 125 c, q 100 fault grading package type 2 pn = 80-pin plastic tqfp pq = 132-pin plastic bumpered qfp pz = 100-pin plastic tqfp c = cmos e = cmos eprom f = flash eeprom lc = low-voltage cmos (3.3 v) vc = low-voltage cmos (3 v) device 'c2xx dsp 209 203 240 241 242 'f2xx dsp 206 240 241 243 (b) bootloader option 2 tqfp = thin quad flat package figure 16. tms320 device nomenclature documentation support extensive documentation supports all of the tms320 family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user's guides for all devices and development-support tools; and hardware and software applications. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support dsp research and education. the tms320 newsletter, details on signal processing , is published quarterly and distributed to update tms320 customers on product information. the tms320 dsp bulletinboard service (bbs) provides access to a wealth of information pertaining to the tms320 family, including documentation, source code, and object code for many dsp algorithms and utilities. the bbs can be reached at 281/274-2323. updated information on the tms320 dsp controllers can be found on the worldwide web at: http://www.ti.com/dsps.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 61 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v dd 3 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : l version 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a version 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s, q versions 40 c to125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 all voltage values are with respect to v ss . recommended operating conditions min nom max unit v dd supply voltage 4.5 5 5.5 v v ss supply ground 0 v xtal1/clkin 3 v dd + 0.3 v ih high-level input voltage poreset , nmi, rs , and trst 2.2 2.5 v dd + 0.3 v all other inputs 2 v dd + 0.3 v il low level in p ut voltage xtal1/clkin 0.3 0.7 v v il lo w- le v el inp u t v oltage all other inputs 0.3 0.8 v rs 19 i oh high-level output current, v oh = 2.4 v see complete listing of pin names ? 16 ma all other outputs 23 rs 8 i ol low-level output current, v ol = 0.6 v see complete listing of pin names ? 7.5 ma all other outputs 14.5 l version 0 70 t a operating free-air temperature a version 40 85 c s, q versions 40 125 t fp flash programming operating temperature, ('f240 only) l, a, s, q versions 40 85 c q ja thermal resistance, junction-to-ambient 40 c/w q jc thermal resistance, junction-to-case 9.9 c/w min value for 'c240 only ? iopa[0:3], scirxd/io, scitxd/io, xint2/io, xint3/io, adcsoc/iopc0, tmrdir/iopb6, tmrclk/iopb7 emu0, emu1/off
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 62 post office box 1443 ? houston, texas 772511443 output current variation with output voltage: spice simulation results condition: temperature voltage : 150 c : 4.5 v table 17. typical output source current vs. output voltage high 24v 30v 35v 40v 2 . 4 v 3 . 0 v 3 . 5 v 4 . 0 v rs 19 ma 16 ma 12 ma 6 ma see complete listing of pin names 2 16 ma 13.5 ma 9.5 ma 5.0 ma all other inputs 23 ma 18.5 ma 13 ma 6.5 ma 2 iopa[0:3], scirxd/io, scitxd/io, xint2/io, xint3/io, adcsoc/iopc0, tmrdir/iopb6, tmrclk/iopb7 emu0, emu1/off table 18. typical output sink current vs. output voltage low 06v 04v 02v 0 . 6 v 0 . 4 v 0 . 2 v rs 8 ma 6 ma 3 ma see complete listing of pin names 2 7.5 ma 5 ma 2.5 ma all other inputs 14.5 ma 10 ma 5.0 ma 2 iopa[0:3], scirxd/io, scitxd/io, xint2/io, xint3/io, adcsoc/iopc0, tmrdir/iopb6, tmrclk/iopb7 emu0, emu1/off electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage 5-v operation, i oh = max 2.4 v v ol low-level output voltage 5-v operation, i ol = max 0.6 v trst pin with internal pulldown 10 500 i i input current (v i = v ss or v dd ) emu0, emu1/off , tms, tck, and tdi, with internal pullup 500 10 m a all other input pins 10 10 i oz output current, high-impedance state (off-state) v o = v dd or 0 v 5 5 m a supply current, operating mode 5-v operation, t c(co) = 50 ns 80 supply current, idle 1 low-power mode 5-v operation, t c(co) = 50 ns 50 ma i dd supply current, idle 2 low-power mode 5-v operation, t c(co) = 50 ns 7 ma supply current, pll power-down mode 5-v operation, t c(co) = 50 ns 1 supply current, osc power-down mode 5-v operation, t c(co) = 50 ns 400 m a c i input capacitance 15 pf c o output capacitance 15 pf i ddp flash programming supply current 5-v operation, t c(co) = 50 ns 10 ma
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 63 post office box 1443 ? houston, texas 772511443 parameter measurement information tester pin electronics v load i ol c t i oh output under test 50 w where: i ol = 2 ma (all outputs) i oh = 300 m a (all outputs) v load = 1.5 v c t = 110-pf typical load-circuit capacitance figure 17. test load circuit signal transition levels the data in this section is shown for the 5-v version ('c2xx). note that some of the signals use different reference voltages, see the recommended operating conditions table. ttl-output levels are driven to a minimum logic-high level of 2.4 v and to a maximum logic-low level of 0.7 v. figure 18 shows the ttl-level outputs. 0.7 v 20% 2.4 v 80% figure 18. ttl-level outputs ttl-compatible output transition times are specified as follows: for a high-to-low transition , the level at which the output is said to be no longer high is below 80% of the total voltage range and lower, and the level at which the output is said to be low is 20% of the total voltage range and lower. for a low-to-high transition , the level at which the output is said to be no longer low is 20% of the total voltage range and higher, and the level at which the output is said to be high is 80% of the total voltage range and higher.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 64 post office box 1443 ? houston, texas 772511443 parameter measurement information figure 19 shows the ttl-level inputs. 0.7 v 10% 2.0 v 90% figure 19. ttl-level inputs ttl-compatible input transition times are specified as follows: for a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower, and the level at which the input is said to be low is 10% of the total voltage range and lower. for a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher, and the level at which the input is said to be high is 90% of the total voltage range and higher.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 65 post office box 1443 ? houston, texas 772511443 parameter measurement information timing parameter symbology timing parameter symbols used are created in accordance with jedec standard 100-a. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: a a[15:0] ms memory strobe pins is , ds , or ps cl xtal1/clkin r ready co clkout/iopc1 rd read cycle or w/r d d[15:0] rs rs or poreset int nmi, xint1, xint2/io, and xint3/io w write cycle or we lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid f fall time x unknown, changing, or don't care level h hold time z high impedance r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing parameters all output signals from the tms320x240 devices (including clkout) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. the signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. for actual cycle examples, see the appropriate cycle description section of this data sheet. external clock signal (toggling 0 5 v) c2 (see note a) c1 (see note a) crystal xtal2 xtal1/clkin xtal1/clkin xtal2 nc see note b notes: a. for the values of c1 and c2, see the crystal manufacturer's specification. b. use this configuration in conjunction with oscbyp pin pulled low. c. texas instruments encourages customers to submit samples of the device to the resonator/crystal vendor for full characterizat ion. figure 20. recommended crystal / clock connection
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 66 post office box 1443 ? houston, texas 772511443 clock options clock options parameter clkmd[1:0] clock-in mode, divide-by-2 00 clock-in mode, divide-by-1 01 pll enabled, divide-by-2 before pll lock 10 pll enabled, divide-by-1 before pll lock 11 timings with the pll circuit disabled parameter test conditions min max unit f x input clock frequency, divide-by-2 mode t a = 40 c to 125 c 0 2 40 mhz f x input clock frequency, divide-by-1 mode t a = 40 c to 125 c 0 2 20 mhz 2 this device utilizes a fully static design and, therefore, can operate with input clock cycle time [t c(ci) ] approaching infinity. the device is characterized at frequencies approaching 0 hz. switching characteristics over recommended operating conditions [h = 0.5 t c(co) ] (see note 1 and figure 21) parameter clock mode min typ max unit t (cpu) cycle time cpuclk clkin divide by 2 2t c(cl) 2 ns t c(cpu) c yc l e ti me, cpuclk clkin divide by 1 t c(cl) ns t (sys) cycle time sysclk cpuclk divide by 2 2t c(cpu) 2 ns t c(sys) c yc l e ti me, sysclk cpuclk divide by 4 3 4t c(cpu) ns t (co) cycle time clkout clkin divide by 2 2t c(cl) 2 ns t c(co) c yc l e ti me, clkout clkin divide by 1 t c(cl) 2 ns t d(cih-co) delay time, xtal1/clkin high to clkout high/low 3 18 32 ns t f(co) fall time, clkout 5 ns t r(co) rise time, clkout 5 ns t w(col) pulse duration, clkout low h10 h6 h1 ns t w(coh) pulse duration, clkout high h+0 h+4 h+8 ns 2 this device utilizes a fully static design and, therefore, can operate with input clock cycle time [t c(ci) ] approaching infinity. the device is characterized at frequencies approaching 0 hz. 3 sysclk is initialized to divide-by-4 mode by any device reset. note 1: timings assume clkout is set to output cpuclk. clkout is initialized to cpuclk by power-on reset. timing requirements over recommended operating conditions (see figure 21) clock-in mode min max unit t (cl) cycle time xtal1/clkin divide by 2 25 2 ns t c(cl) c yc l e ti me, xtal1/clkin divide by 1 50 2 ns t f(cl) fall time, xtal1/clkin 5 ns t r(cl) rise time, xtal1/clkin 5 ns t w(cil) pulse duration, xtal1/clkin low as a percentage of t c(cl) 45 55 % t w(cih) pulse duration, xtal1/clkin high as a percentage of t c(cl) 45 55 % 2 this device utilizes a fully static design and, therefore, can operate with input clock cycle time [t c(ci) ] approaching infinity. the device is characterized at frequencies approaching 0 hz.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 67 post office box 1443 ? houston, texas 772511443 clock options (continued) t r(co) t f(co) t w(coh) clkout/iopc1 xtal1/clkin t w(col) t d(cihco) t f(ci) t r(ci) t w(cil) t w(cih) t c(co) t c(ci) figure 21. external divide-by-two clock timings external reference crystal with pll-circuit-enabled clock option the internal oscillator is enabled by connecting oscbyp to v dd and connecting a crystal across xtal1/clkin and xtal2 pins as shown in figure 20. the crystal should be in either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30 and a power dissipation of 1 mw; it should be specified at a load capacitance of 20 pf. note that overtone crystals require an additional tuned-lc circuit. timings with the pll circuit enabled parameter external reference crystal min typ max unit 4 mhz 4 f x input clock frequency 6 mhz 6 mhz qy 8 mhz 8 c1, c2 load capacitance 10 pf
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 68 post office box 1443 ? houston, texas 772511443 switching characteristics over recommended operating conditions [h = 0.5 t c(co) ] (see figure 22) parameter clock mode min typ max unit before pll lock, clkin divide by 2 2t c(cl) 2 t c(cpu) cycle time, cpuclk before pll lock, clkin divide by 1 t c(cl) ns after pll lock 50 t (sys) cycle time sysclk cpuclk divide by 2 2t c(cpu) 2 ns t c(sys) c yc l e ti me, sysclk cpuclk divide by 4 3 4t c(cpu) ns t c(co) cycle time, clkout 50 2 ns t f(co) fall time, clkout 5 ns t r(co) rise time, clkout 5 ns t w(col) pulse duration, clkout low h10 h6 h1 ns t w(coh) pulse duration, clkout high h+0 h+4 h+8 ns t transition time, pll s y nchronized after before pll lock, clkin divide by 2 2000t c(cl) ns t p ,y pll enabled before pll lock, clkin divide by 1 1000t c(cl) ns 2 this device utilizes a fully static design and, therefore, can operate with input clock cycle time [t c(ci) ] approaching infinity. the device is characterized at frequencies approaching 0 hz. 3 sysclk is initialized to divide-by-4 mode by any device reset. timing requirements over recommended operating conditions (see note 1 and figure 22) external reference crystal min max unit 4 mhz 250 2 t c(cl) cycle time, xtal1/clkin 6 mhz 167 ns () y 8 mhz 125 t f(cl) fall time, xtal1/clkin 5 ns t r(cl) rise time, xtal1/clkin 5 ns t w(cil) pulse duration, xtal1/clkin low as a percentage of t c(ci) 40 60 % t w(cih) pulse duration, xtal1/clkin high as a percentage of t c(ci) 40 60 % 2 this device utilizes a fully static design and, therefore, can operate with input clock cycle time [t c(ci) ] approaching infinity. the device is characterized at frequencies approaching 0 hz. note 1: timings assume clkout is set to output cpuclk. clkout is initialized to cpuclk by power-on reset. xtal1/clkin t c(ci) t w(cil) t w(cih) t w(col) t w(coh) t c(co) t f(cl) t r(cl) t r(co) t f(co) clkout figure 22. clkin-to-clkout timings for pll oscillator mode, multiply-by-5 option with 4-mhz crystal
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 69 post office box 1443 ? houston, texas 772511443 low-power mode timings switching characteristics over recommended operating conditions [h = 0.5 t c(co) ] (see figure 23, figure 24, figure 25, and figure 26) parameter low-power modes min typ max unit t d(wake a) dela y time, clkout switchin g to idle 1 and idle 2 15 x t c(co) ns t d(wake-a) y, g program execution resume (see note 1) pll or osc power down 15 x t c(ci) ns t d(idle-coh) delay time, idle instruction executed to clkout high (see note 1) idle 2, pll power down, osc power down 500 ns t d(wake-lock) delay time, clkout switching to pll synchronized (see note 1) pll or osc power down 100 m s t d(wake-osc) delay time, wakeup interrupt asserted to oscillator running osc power down 10 ms t d(idle-osc) delay time, idle instruction executed to oscillator power off osc power down 60 m s note 1: timings assume clkout is set to output cpuclk. clkout is initialized to cpuclk by power-on reset. wake int clkout/iopc1 a0a15 t d(wakea) figure 23. idle1 entry and exit timings t d(wakea) t d(idlecoh) wake int clkout/iopc1 a0a15 figure 24. idle2 entry and exit timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 70 post office box 1443 ? houston, texas 772511443 low-power mode timings (continued) wake int clkout/iopc1 a0a15 t d(idlecoh) t d(wakelock) t d(wakea) figure 25. pll power-down entry and exit timings t d(wakea) t d(wakelock) t d(wakeosc) t d(idlecoh) t d(idleosc) wake int clkout/iopc1 a0a15 figure 26. osc power-down entry and exit timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 71 post office box 1443 ? houston, texas 772511443 memory and peripheral interface timings memory and parallel i/o interface read timings switching characteristics over recommended operating conditions for a memory read @ 5 v [h = 0.5t c(co) ] (see figure 27) parameter min max unit t d(co-a)rd delay time, clkout/iopc1 low to address valid 17 ns t d(co-sl)rd delay time, clkout/iopc1 low to strb low 10 ns t d(co-sh)rd delay time, clkout/iopc1 low to strb high 6 ns t d(co-actl)rd delay time, clkout/iopc1 low to ps , ds , is , and br low 10 ns t d(co-acth)rd delay time, clkout/iopc1 low to ps , ds , is , and br high 10 ns timing requirements over recommended operating conditions for a memory read @ 5 v [h = 0.5t c(co) ] 2 (see figure 27) min max unit t (a) access time from address valid to read data 0 wait state 2h 32 ns t a(a) a ccess ti me, f rom a dd ress va lid t o rea d d a t a 1 wait state 4h 32 ns t su(d-col)rd setup time, data read before clkout/iopc1 low 15 ns t h(col-d)rd hold time, data read after clkout/iopc1 low 2 ns 2 all timings with respect to clkout/iopc1 assume clksrc[1:0] bits are set to select cpuclk for output.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 72 post office box 1443 ? houston, texas 772511443 memory and peripheral interface timings (continued) memory and parallel i/o interface read timings (continued) ps , ds , is , or br t d(coa)rd t d(coa)rd t a(a) t su(d-col)rd t h(col-d)rd clkout/iopc1 a0a15 w/r d0d15 we ready strb t d(coactl)rd t d(cosl)rd t d(cosh)rd t d(coacth)rd figure 27. memory interface read timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 73 post office box 1443 ? houston, texas 772511443 memory and peripheral interface timings (continued) memory and parallel i/o interface write timings switching characteristics over recommended operating conditions for a memory write @ 5 v [h = 0.5t c(co) ] 2 (see figure 28) parameter min max unit t d(co-a)w delay time, clkout/iopc1 high to address valid 17 ns t d(co-d) delay time, clkout/iopc1 low to data bus driven 15 ns t h(wh-a) hold time, address valid after we high h 8 h 10 3 ns t w(wh) pulse duration, we high 2h 11 ns t w(wl) pulse duration, we low 2h 11 t d(co-wl) delay time, clkout/iopc1 low to we low 9 ns t d(co-wh) delay time, clkout/iopc1 low to we high 9 ns t su(d-wh) setup time, write data valid before we high 2h 8 ns t hz(wh-d) high-impedance time, we high to data bus hi-z 0 5 ns t d(co-sl)w delay time, clkout/iopc1 low to strb low 10 ns t d(co-sh)w delay time, clkout/iopc1 low to strb high 6 ns t d(co-actl)w delay time, clkout/iopc1 high to ps , ds , is , and br low 10 ns t d(co-acth)w delay time, clkout/iopc1 high to ps , ds , is , and br high 10 ns t d(co-rwl) delay time, clkout/iopc1 high to r/w low 10 ns t d(co-rwh) delay time, clkout/iopc1 high to r/w high 10 ns 2 all timings with respect to clkout/iopc1 assume clksrc[1:0] bits are set to select cpuclk for output. 3 min value for 'c240 only
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 74 post office box 1443 ? houston, texas 772511443 memory and peripheral interface timings (continued) memory and parallel i/o interface write timings (continued) ps , ds , is , or br clkout/iopc1 a0a15 r/w d0d15 we ready strb t d(coa)w t d(coacth)w t h(wh-a) t d(cowh) t hz(wh-d) t d(cod) t d(cosl)w t w(wh) t su(d-wh) t d(coactl)w t d(cowl) t d(cosh)w t d(corwl) t d(corwh) w/r figure 28. memory interface write timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 75 post office box 1443 ? houston, texas 772511443 i/o timing variation with load capacitance: spice simulation results 2.2 v 0.8 v condition: temperature capacitance voltage : 40 to 150 c : 5 125pf : 5.0 v figure 29. rise and fall time diagram table 19. timing variation with load capacitance: [v cc = 5 v, v oh = 2.2 v, v ol = 0.8 v] 40 c 27 c 150 c rise fall rise fall rise fall 5 pf 2.5 ns 3.6 ns 3.1 ns 4.5 ns 4.3 ns 6.2 ns 25 pf 3.1 ns 4.6 ns 4.0 ns 5.7 ns 5.6 ns 7.8 ns 50 pf 3.9 ns 5.9 ns 5.0 ns 7.3 ns 7.2 ns 9.9 ns 75 pf 4.7 ns 7.3 ns 6.1 ns 8.9 ns 8.8 ns 11.7 ns 100 pf 5.4 ns 8.9 ns 7.2 ns 10.6 ns 10.5 ns 13.8 ns 125 pf 6.2 ns 10.4 ns 8.3 ns 12.2 ns 12.1 ns 15.8 ns
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 76 post office box 1443 ? houston, texas 772511443 ready timings timing requirements over recommended operating conditions [h = 0.5t c(co) ] 2 (see figure 30) min max unit t su(r-co) setup time, ready low before clkout/iopc1 high 14 16 3 ns t h(co-r) hold time, ready low after clkout/iopc1 high 0 ns t v(r)ard valid time, ready after address valid on read 3h 31 3h 33 ns t v(r)aw valid time, ready after address valid on write 4h 31 4h 33 ns 2 the ready timings are based on one software wait state. at full speed operation, the 'x240 does not allow for single ready-base d wait states. 3 min value for 'c240 only max values for 'c240 only ps , ds , or is clkout/iopc1 a0a15 w/r d0d15 we ready strb t v(r)aw t h(cor) t su(rco) t v(r)ard figure 30. ready timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 77 post office box 1443 ? houston, texas 772511443 rs and poreset timings switching characteristics over recommended operating conditions for a reset [h = 0.5t c(co) ] (see figure 31 and figure 32) parameter min max unit t w(rsl1) pulse duration, rs low 2 8t c(sys) ns t d(rs) delay time, rs low to program address at reset vector 4h ns t d(ex) delay time, rs high to reset vector executed 32h ns 2 the parameter t w(rsl1) refers to the time rs is an output. timing requirements over recommended operating conditions for a reset [h = 0.5t c(co) ] (see figure 31 and figure 32) min max unit t w(rsl) pulse duration, rs or poreset low 3 5 ns 3 the parameter t w(rsl) refers to the time rs is an input. xtal1/clkin v cc rs 3 poreset 2 2 poreset is required to be driven low during power up to ensure all clock/pll registers are reset to a known state. 3 rs is a bidirectional (open-drain output) pin and can be optionally pulled low through an open-drain or open-collector drive circ uit, or through a 2.7-k w resistor in series with a totem pole drive circuit. if rs is left undriven, then a 20-k w pullup resistor should be used. figure 31. reset timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 78 post office box 1443 ? houston, texas 772511443 rs and poreset timings (continued) 0000h 0001h t w(rsl1) t d(rs) t d(ex) t w(rsl) a0a15 rs 2 poreset 2 rs is driven low by any device reset, which includes asserting poreset , rs , access to an illegal address, execution of a software reset, or a watchdog timer reset. figure 32. power-on reset timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 79 post office box 1443 ? houston, texas 772511443 xf, bio , and mp/mc timings switching characteristics over recommended operating conditions [h = 0.5t c(co) ] (see figure 33) parameter min max unit t d(xf) delay time, clkout high to xf high/low 11 ns timing requirements over recommended operating conditions [h = 0.5t c(co) ] (see figure 33) min max unit t w(biol) pulse duration, bio low 2h + 16 ns t w(mpmcv) pulse duration, mp/mc valid 2 2h + 24 ns 2 this is the minimum time the mp/mc pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip. t d(xf) xf bio clkout/iopc1 t w(biol) mp/mc t w(mpmcv) 2 2 this is the minimum time the mp/mc pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip. valid figure 33. xf, bio , and mp/mc timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 80 post office box 1443 ? houston, texas 772511443 timing event manager interface pwm/cmp timings pwm refers to pwm1/cmp1, pwm2/cmp2, pwm3/cmp3, pwm4/cmp4, pwm5/cmp5, pwm6/cmp6, t1pwm/t1cmp, t2pwm/t2cmp, t3pwm/t3cmp, pwm7/cmp7, pwm8/cmp8, and pwm9/cmp9. switching characteristics over recommended operating conditions for pwm timing [h = 0.5t c(co) ] (see figure 34) parameter min max unit t d(pwm)co delay time, clkout high to pwm output switching 12 ns timing requirements over recommended operating conditions for pwm timing [h = 0.5t c(co) ] (see figure 35 and figure 36) min max unit t w(tmrdir) pulse duration, tmrdir low/high 4h + 12 4h + 14 2 ns t w(tmrclkl) pulse duration, tmrclk low as a percentage of tmrclk cycle time 40 60 % t w(tmrclkh) pulse duration, tmrclk high as a percentage of tmrclk cycle time 40 60 % t c(tmrclk) cycle time, tmrclk 4 t c(cpu) ns 2 min value for 'c240 only t d(pwm)co pwm clkout/iopc1 figure 34. pwm and compare output timings t w(tmrclkl) tmrclk t c(tmrclk) t w(tmrclkh) figure 35. external timer clock input timings t w(tmrdir) tmrdir figure 36. external timer direction input timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 81 post office box 1443 ? houston, texas 772511443 capture and qep timings cap refers to cap1/qep1/iopc4, cap2/qep2/iopc5, cap3/iopc6, and cap4/iopc7. timing requirements over recommended operating conditions for cap [h = 0.5t c(co) ] (see figure 37) min max unit t w(cap) pulse duration, cap input low/high 4h + 12 4h + 15 2 ns 2 min value for 'c240 only cap t w(cap) figure 37. capture and qep input timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 82 post office box 1443 ? houston, texas 772511443 interrupt timings pwm refers to pwm1/cmp1, pwm2/cmp2, pwm3/cmp3, pwm4/cmp4, pwm5/cmp5, pwm6/cmp6, t1pwm/t1cmp, t2pwm/t2cmp, t3pwm/t3cmp, pwm7/cmp7, pwm8/cmp8, and pwm9/cmp9. int refers to nmi, xint1, xint2/io, and xint3/io. pdp refers to pdpint . switching characteristics over recommended operating conditions for interrupts [h = 0.5t c(co) ] (see figure 39) parameter min max unit t d(pwm)pdp delay time, pdpint low to pwm to high-impedance state 0 15 ns timing requirements over recommended operating conditions for interrupts [h = 0.5t c(co) ] (see figure 38 and figure 39) min max unit t w(int) pulse duration, int input low/high t c(sys) + 12 ns t w(pdp) pulse duration, pdpint input low 2h + 18 ns t d(int) delay time, int low/high to interrupt-vector fetch 2t c(sys) + 4t c(cpu) ns t w(int) int figure 38. external interrupt timings pwm pdpint t w(pdp) t d(pwm)pdp figure 39. power-drive protection interrupt timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 83 post office box 1443 ? houston, texas 772511443 general-purpose input/output timings gpo refers to the digital output function of shared pins iopa03, iopb07, iopc07, xint2/io, xint3/io. gpi refers to the digital input function of shared pins iopa03, iopb07, iopc07, xint2/io, xint3/io. switching characteristics over recommended operating conditions for a gpi/o [h = 0.5t c(co) ] (see figure 40) parameter min max unit t d(gpo)co dela y time, clkout low to gpo low/hi g h xint2/io, xint3/io, iopb6, iopb7, and iopc0 33 ns d(gpo)co y, g all other gpos 25 timing requirements over recommended operating conditions for a gpi/o [h = 0.5t c(co) ] (see figure 41) min max unit t w(gpi) pulse duration, gpi high/low t c(sys) + 12 ns t d(gpo)co gpo clkout/iopc1 figure 40. general-purpose output timings gpi t w(gpi) figure 41. general-purpose input timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 84 post office box 1443 ? houston, texas 772511443 serial communications interface (sci) i/o timings timing characteristics for sci (see note 2 and figure 42) parameter (brr + 1) is even and brr = 0 (brr + 1) is odd and brr 0 unit min max min max t c(scc) cycle time, sciclk 16t c 65 536t c 24t c 65 535t c ns t v(txd) valid time, scitxd data t c(scc) 70 t c(scc) +70 t c(scc) 70 t c(scc) +70 ns t v(rxd) valid time, scirxd data 16t c 24t c ns note 2: t c = system clock cycle time = 1/sysclk = t c(sys) t v(txd) t v(rxd) data valid data valid scitxd scirxd figure 42. sci timings
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 post office box 1443 houston, texas 772511443 ? 85 spi master mode timing parameters spi master mode timing information is listed in the following tables. spi master mode external timing parameters (clock phase = 0) 2 (see figure 43) when (spibrr + 1) is even or spibrr = 0 or 2 when (spibrr + 1) is odd and spibrr > 3 unit min max min max t c(spc)m cycle time, spiclk 4t c 3 128t c 3 5t c 3 127t c 3 ns t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m 0.5t c 70 0.5t c(spc)m 0.5t c ns t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m 0.5t c 70 0.5t c(spc)m 0.5t c ns t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m + 0.5t c 70 0.5t c(spc)m + 0.5t c ns t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m + 0.5t c 70 0.5t c(spc)m + 0.5t c ns t d(spch-simo)m delay time, spiclk high (clock polarity = 0) to spisimo valid 10 10 10 10 ns t d(spcl-simo)m delay time, spiclk low (clock polarity = 1) to spisimo valid 10 10 10 10 ns t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity =0) 0.5t c(spc)m 70 0.5t c(spc)m + 0.5t c 70 ns t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity =1) 0.5t c(spc)m 70 0.5t c(spc)m + 0.5t c 70 ns t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 0) 0 0 ns t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 1) 0 0 ns t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 0) 0.25t c(spc)m 70 0.5t c(spc)m 0.5t c 70 ns t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 1) 0.25t c(spc)m 70 0.5t c(spc)m 0.5t c 70 ns 2 the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is cleared. 3 t c = system clock cycle time = 1 / sysclk = t c(sys) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 86 post office box 1443 ? houston, texas 772511443 parameter measurement information t d(spch-simo)m t d(spcl-simo)m spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid t w(spcl)m t w(spcl)m t c(spc)m spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. t w(spch)m t w(spch)m t v(spch-simo)m t v(spcl-simo)m t su(somi-spcl)m t su(somi-spch)m t v(spcl-somi)m t v(spch-somi)m figure 43. spi master mode external timings (clock phase = 0)
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 post office box 1443 houston, texas 772511443 ? 87 spi master mode external timing parameters (clock phase = 1) 2 (see figure 44) when (spibrr + 1) is even or spibrr = 0 or 2 when (spibrr + 1) is odd and spibrr > 3 unit min max min max t c(spc)m cycle time, spiclk 4t c 3 128t c 3 5t c 3 127t c 3 ns t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m 0.5t c 70 0.5t c(spc)m 0.5t c ns t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m 0.5t c 70 0.5t c(spc)m 0.5t c t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m + 0.5t c 70 0.5t c(spc)m + 0.5t c t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m 70 0.5t c(spc)m 0.5t c(spc)m + 0.5t c 70 0.5t c(spc)m + 0.5t c ns t su(simo-spch)m setup time, spisimo data valid before spiclk high (clock polarity = 0) 0.5t c(spc)m 70 0.5t c(spc)m 70 ns t su(simo-spcl)m setup time, spisimo data valid before spiclk low (clock polarity = 1) 0.5t c(spc)m 70 0.5t c(spc)m 70 ns t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity =0) 0.5t c(spc)m 70 0.5t c(spc)m 70 ns t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity =1) 0.5t c(spc)m 70 0.5t c(spc)m 70 ns t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 0) 0 0 ns t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 1) 0 0 ns t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 0) 0.25t c(spc)m 70 0.5t c(spc)m 70 ns t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 1) 0.25t c(spc)m 70 0.5t c(spc)m 70 ns 2 the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is set. 3 t c = system clock cycle time = 1 / sysclk = t c(sys) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 88 post office box 1443 ? houston, texas 772511443 parameter measurement information data valid t v(spch-somi)m t v(spcl-somi)m spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid t c(spc)m t w(spch)m t w(spcl)m spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. t su(simo-spch)m t su(simo-spcl)m t v(spch-simo)m t v(spcl-simo)m t su(somi-spch)m t su(somi-spcl)m t w(spch)m t w(spcl)m figure 44. spi master mode external timings (clock phase = 1)
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 89 post office box 1443 ? houston, texas 772511443 spi slave mode timing parameters slave mode timing information is listed in the following tables. spi slave mode external timing parameters (clock phase = 0) 2 (see figure 45) min max unit t c(spc)s cycle time, spiclk 8t c 3 ns t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s 70 0.5t c(spc)s ns t d(spch-somi)s delay time, spiclk high (clock polarity = 0) to spisomi valid 0.375t c(spc)s 70 ns t d(spcl-somi)s delay time, spiclk low (clock polarity = 1) to spisomi valid 0.375t c(spc)s 70 ns t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =0) 0.75t c(spc)s ns t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =1) 0.75t c(spc)s ns t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 0) 0 ns t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 1) 0 ns t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)s ns t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)s ns 2 the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is cleared. 3 t c = system clock cycle time = 1 / sysclk = t c(sys) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 90 post office box 1443 ? houston, texas 772511443 parameter measurement information t d(spch-somi)s t d(spcl-somi)s spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid t w(spch)s t w(spcl)s t c(spc)s spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. t v(spcl-somi)s t v(spch-somi)s t su(simo-spcl)s t su(simo-spch)s t v(spcl-simo)s t v(spch-simo)s t w(spch)s t w(spcl)s figure 45. spi slave mode external timing (clock phase = 0)
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 91 post office box 1443 ? houston, texas 772511443 spi slave mode external timing parameters (clock phase = 1) 2 (see figure 46) min max unit t c(spc)s cycle time, spiclk 8t c 3 ns t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s 70 0.5t c(spc)s ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s 70 0.5t c(spc)s ns t su(somi-spch)s setup time, spisomi before spiclk high (clock polarity = 0) 0.125t c(spc)s ns t su(somi-spcl)s setup time, spisomi before spiclk low (clock polarity = 1) 0.125t c(spc)s ns t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =0) 0.75t c(spc)s ns t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =1) 0.75t c(spc)s ns t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 0) 0 ns t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 1) 0 ns t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)s ns t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)s ns 2 the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is set. 3 t c = system clock cycle time = 1 / sysclk = t c(sys) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 92 post office box 1443 ? houston, texas 772511443 parameter measurement information data valid spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid t c(spc)s t w(spch)s t w(spcl)s spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. t su(somi-spch)s t su(somi-spcl)s t v(spch-somi)s t v(spcl-somi)s t su(simo-spch)s t su(simo-spcl)s t v(spch-simo)s t v(spcl-simo)s t w(spch)s t w(spcl)s figure 46. spi slave mode external timing (clock phase = 1)
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 93 post office box 1443 ? houston, texas 772511443 10-bit dual analog-to-digital converter (adc) the 10-bit dual adc has a separate power bus for its analog circuitry. these pins are referred to as v cca and v ssa . the purpose is to enhance adc performance by preventing digital switching noise of the logic circuitry that can be present on v ss and v cc from coupling into the adc analog stage. all adc specifications are given with respect to v ssa unless otherwise noted. resolution 10-bit (1024 values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . monotonic assured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output conversion mode 000h to 3ffh (000h for v i v ssa ; 3ffh for v i v cca ) . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions min nom max unit v cca analog supply voltage 4.5 5 5.5 v v ssa analog ground 0 v v refhi analog supply reference source 2 v reflo v cca v v reflo analog ground reference source 2 v ssa v refhi v v ai analog input voltage, adcin0adcin15 v ssa v cca v 2 v refhi and v reflo must be stable, within 1/2 lsb of the required resolution, during the entire conversion time.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 94 post office box 1443 ? houston, texas 772511443 operating characteristics over recommended operating condition ranges 2 parameter description min max unit v cca =55v converting 5 i cca analog su pp ly current v cca = 5 . 5 v non-converting 2 ma i cca analog su ly current v cca = v refhi = 5.5 v pll or osc power down 1 ma i ref input charge current, v refhi or v reflo v cca = v ccd = v refhi = 5.5 v, v reflo = 0 v 5 ma c i analog in p ut ca p acitance typical capacitive load on non-sampling 6 p f c ai analog inp u t capacitance y analog input pin sampling 8 pf z ai analog input source impedance analog input source impedance for conversions to remain within specifications. 9 k w e dnl differential nonlinearity error difference between the actual step width and the ideal value 1 1.5 lsb e inl integral nonlinearity error maximum deviation from the best straight line through the adc transfer characteristics, excluding the quantization error 1.5 lsb t d(pu) delay time, power-up to adc valid time to stabilize analog stage after power-up 10 s 2 absolute resolution = 4.89 mv. at v refhi = 5 v and v reflo = 0 v, this is one lsb. as v refhi decreases, v reflo increases, or both, the lsb sizes decrease. therefore, the absolute accuracy and differential/integral linearity errors in terms of lsbs increase. the adc module allows complete freedom in the design of the sources for the analog inputs. the period of the sample time is independent of the source impedance. the sample-and-hold period occurs in the first half-period of the adc clock after the adcimstart bit or the adcsoc bit of the adc control register 1 (adctrl1, bits 13 and 0, respectively) is set to 1. the conversion then occurs during the next six adc clock cycles. the digital result registers are updated on the next adc clock cycle once the conversion is completed. adc input pin circuit one of the most common a/d application errors is inappropriate source impedance. in practice, minimum source impedance should be used to limit the error as well as minimize the required sampling time; however, the source impedance must be smaller than z ai . a typical adc input pin circuit is shown in figure 47. v in r1 r equiv v ai (to adcinx input) r1 = 9 k w typical figure 47. typical adc input pin circuit
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 95 post office box 1443 ? houston, texas 772511443 adc timing requirements (see figure 48) min max unit t c(ad) cycle time, adc prescaled clock 1 s t w(shc) pulse duration, total sample/hold and conversion time (see note 3) 6.1 s t w(sh) pulse duration, sample and hold time t c(ad) s t su(sh) setup time, analog input stable before sample/hold start 0 ns t h(sh) hold time, analog input stable after sample/hold complete 0 ns t w(c) pulse duration, total conversion time 4.5t c(ad) s t d(soc-sh) delay time, start of conversion 2 to beginning of sample and hold 3t c(sys) ns t d(eoc-fifo) delay time, end of conversion to data loaded into result fifo 3t c(sys) ns 2 start of conversion is signaled by the adcimstart bit or the adcsoc bit set in software, the external start signal active (adcs oc), or internal evsoc signal active. note 3: the total sample/hold and conversion time is determined by the summation of t d(soc-sh) , t w(sh ), t w(c) , and t d(eoc-fifo) . 0 3 2 4 5 1 t w(c) t d(eocfifo) 6 7 8 9 t h(sh) t w(sh) t su(sh) t c(ad) adc clock analog input bit converted t d(socsh) convert internal start start of convert xfr to fifo sample/hold t w(shc) figure 48. analog-to-digital timing
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 96 post office box 1443 ? houston, texas 772511443 flash eeprom switching characteristics over recommended operating conditions parameter '320f240 unit parameter min typ max unit program-erase endurance 10k cycles program pulses per word 2 1 10 150 pulses erase pulses per array 2 1 20 1000 pulses flash-write pulses per array 2 1 20 6000 pulses 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282). timing requirements over recommended operating conditions '320f240 unit min max unit t d(busy) delay time, after mode deselect to stabilization 2 10 m s t d(rd-verify) delay time, verify read mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282). programming operation parameter '320f240 unit parameter min nom max unit t w(pgm) pulse duration, programming algorithm 2 95 100 105 m s t d(pgm-mode) delay time, program mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282). erase operation parameter '320f240 unit parameter min nom max unit t w(erase) pulse duration, erase algorithm 2 6.65 7 7.35 ms t d(erase-mode) delay time, erase mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282). flash-write operation parameter '320f240 unit parameter min nom max unit t w(flw) pulse duration, flash-write algorithm 23 13.3 14 14.7 ms t d(flw-mode) delay time, flash-write mode select to stabilization 23 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/f24x dsps embedded flash memory technical reference (literature number spru282). 3 refer to the recommended operating conditions section for the flash programming operating temperature range when programming flash.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 97 post office box 1443 ? houston, texas 772511443 register file compilation table 20 is a collection of all the programmable registers of the tms320x240 (provided for a quick reference). table 20. register file compilation addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data memory space cpu status registers arp ov ovm 1 intm dp(8) st0 dp(7) dp(6) dp(5) dp(4) dp(3) dp(2) dp(1) dp(0) st0 arb cnf tc sxm c 1 st1 1 1 1 xf 1 1 pm st1 global memory and cpu interrupt registers 00004h e e e e e e e e imr 00004h e e int6 mask int5 mask int4 mask int3 mask int2 mask int1 mask imr 00005h e e e e e e e e greg 00005h global data memory configuration bits (70) greg 00006h e e e e e e e e ifr 00006h e e int6 flag int5 flag int4 flag int3 flag int2 flag int1 flag ifr system configuration registers 07018h reset1 reset0 e e e e e e syscr 07018h clksrc1 clksrc0 e e e e e e syscr 07019h reserved 0701ah porst e e illadr e swrst wdrst e syssr 0701ah e e hpo e vccaor e e vecrd syssr 0701bh to 0701dh reserved 0701eh 0 0 0 0 0 0 0 0 sysivr 0701eh d7 d6 d5 d4 d3 d2 d1 d0 sysivr 0701fh reserved wd/rti control registers 07020h reserved 07021h d7 d6 d5 d4 d3 d2 d1 d0 rticntr 07022h reserved 07023h d7 d6 d5 d4 d3 d2 d1 d0 wdcntr 07024h reserved 07025h d7 d6 d5 d4 d3 d2 d1 d0 wdkey 07026h reserved 07027h rti flag rti ena e e e rtips2 rtips1 rtips0 rticr 07028h reserved 07029h wd flag wddis wdchk2 wdchk1 wdchk0 wdps2 wdps1 wdps0 wdcr pll clock control registers 0702ah reserved 0702bh clkmd(1) clkmd(0) pllock(1) pllock(0) pllpm(1) pllpm(0) aclkena pllps ckcr0 0702ch reserved
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 98 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll clock control registers (continued) 0702dh ckinf(3) ckinf(2) ckinf(1) ckinf(0) plldiv(2) pllfb(2) pllfb(1) pllfb(0) ckcr1 0702eh to 07031h reserved a-to-d module control registers 07032h suspend- soft suspend- free adcim- start adc1en adc2en adccon- run adcinten adcintflag adctrl1 adceoc adc2chsel adc1chsel adcsoc 07033h reserved 07034h e e e e e adcevsoc adcextsoc e adctrl2 07034h adcfifo1 e adcfifo2 adcpscale adctrl2 07035h reserved 07036h d9 d8 d7 d6 d5 d4 d3 d2 adcfifo1 07036h d1 d0 0 0 0 0 0 0 adcfifo1 07037h reserved 07038h d9 d8 d7 d6 d5 d4 d3 d2 adcfifo2 07038h d1 d0 0 0 0 0 0 0 adcfifo2 07039h to 0703fh reserved serial peripheral interface (spi) configuration control registers 07040h spi sw reset clock polarity e e e spi char2 spi char1 spi char0 spiccr 07041h e e e overrun int ena clock phase master/ slave talk spi int ena spictl 07042h receiver overrun spi int flag e e e e e e spists 07043h reserved 07044h e spi bit rate 6 spi bit rate 5 spi bit rate 4 spi bit rate 3 spi bit rate 2 spi bit rate 1 spi bit rate 0 spibrr 07045h reserved 07046h ercvd7 ercvd6 ercvd5 ercvd4 ercvd3 ercvd2 ercvd1 ercvd0 spiemu 07047h rcvd7 rcvd6 rcvd5 rcvd4 rcvd3 rcvd2 rcvd1 rcvd0 spibuf 07048h reserved 07049h sdat7 sdat6 sdat5 sdat4 sdat3 sdat2 sdat1 sdat0 spidat 0704ah to 0704ch reserved 0704dh spiste data in spiste data out spiste function spiste data dir spiclk data in spiclk data out spiclk function spiclk data dir spipc1 0704eh spisimo data in spisimo data out spisimo function spisimo data dir spisomi data in spisomi data out spisomi function spisomi data dir spipc2 0704fh e spi priority spi espen e e e e e spipri
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 99 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 serial communications interface (sci) configuration control registers 07050h stop bits even/odd parity parity enable sci ena addr/idle mode sci char2 sci char1 sci char0 sciccr 07051h e rx err int ena sw reset clock ena txwake sleep txena rxena scictl1 07052h baud15 (msb) baud14 baud13 baud12 baud11 baud10 baud9 baud8 scihbaud 07053h baud7 baud6 baud5 baud4 baud3 baud2 baud1 baud0 (lsb) scilbaud 07054h txrdy tx empty e e e e rx/bk int ena tx int ena scictl2 07055h rx error rxrdy brkdt fe oe pe rxwake e scirxst 07056h erxdt7 erxdt6 erxdt5 erxdt4 erxdt3 erxdt2 erxdt1 erxdt0 scirxemu 07057h rxdt7 rxdt6 rxdt5 rxdt4 rxdt3 rxdt2 rxdt1 rxdt0 scirxbuf 07058h reserved 07059h txdt7 txdt6 txdt5 txdt4 txdt3 txdt2 txdt1 txdt0 scitxbuf 0705ah to 0705dh reserved 0705eh scitxd data in scitxd data out scitxd function scitxd data dir scirxd data in scirxd data out scirxd function scirxd data dir scipc2 0705fh e scitx priority scirx priority sci espen e e e e scipri 07060h to 0706fh reserved external interrupt control registers 07070h xint1 flag e e e e e e e xint1cr 07070h e xint1 pin data 0 e e xint1 polarity xint1 priority xint1 ena xint1cr 07071h reserved 07072h nmi flag e e e e e e e nmicr 07072h e nmi pin data 1 e e nmi polarity e e nmicr 07073h to 07077h reserved 07078h xint2 flag e e e e e e e xint2cr 07078h e xint2 pin data e xint2 data dir xint2 data out xint2 polarity xint2 priority xint2 ena xint2cr 07079h reserved
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 100 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 external interrupt control registers (continued) 0707ah xint3 flag e e e e e e e xint3cr 0707ah e xint3 pin data e xint3 data dir xint3 data out xint3 polarity xint3 priority xint3 ena xint3cr 0707bh to 0708fh reserved digital i/o control registers 07090h cra.15 cra.14 cra.13 cra.12 cra.11 cra.10 cra.9 cra.8 ocra 07090h e e e e cra.3 cra.2 cra.1 cra.0 ocra 07091h reserved 07092h e e e e e e e e ocrb 07092h crb.7 crb.6 crb.5 crb.4 crb.3 crb.2 crb.1 crb.0 ocrb 07093h to 07097h reserved 07098h e e e e a3dir a2dir a1dir a0dir padatdir 07098h e e e e iopa3 iopa2 iopa1 iopa0 padatdir 07099h reserved 0709ah b7dir b6dir b5dir b4dir b3dir b2dir b1dir b0dir pbdatdir 0709ah iopb7 iopb6 iopb5 iopb4 iopb3 iopb2 iopb1 iopb0 pbdatdir 0709bh reserved 0709ch c7dir c6dir c5dir c4dir c3dir c2dir c1dir c0dir pcdatdir 0709ch iopc7 iopc6 iopc5 iopc4 iopc3 iopc2 iopc1 iopc0 pcdatdir 0709dh to 073ffh reserved general-purpose (gp) timer configuration control registers 07400h t3stat t2stat t1stat t3toadc t2toadc t1toadc(1) gptcon 07400h t1toadc(0) tcompoe t3pin t2pin t1pin gptcon 07401h d15 d14 d13 d12 d11 d10 d9 d8 t1cnt 07401h d7 d6 d5 d4 d3 d2 d1 d0 t1cnt 07402h d15 d14 d13 d12 d11 d10 d9 d8 t1cmpr 07402h d7 d6 d5 d4 d3 d2 d1 d0 t1cmpr 07403h d15 d14 d13 d12 d11 d10 d9 d8 t1pr 07403h d7 d6 d5 d4 d3 d2 d1 d0 t1pr 07404h free soft tmode2 tmode1 tmode0 tps2 tps1 tps0 t1con 07404h tswt1 tenable tclks1 tclks0 tcld1 tcld0 tecmpr selt1pr t1con 07405h d15 d14 d13 d12 d11 d10 d9 d8 t2cnt 07405h d7 d6 d5 d4 d3 d2 d1 d0 t2cnt 07406h d15 d14 d13 d12 d11 d10 d9 d8 t2cmpr 07406h d7 d6 d5 d4 d3 d2 d1 d0 t2cmpr
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 101 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general-purpose (gp) timer configuration control registers (continued) 07407h d15 d14 d13 d12 d11 d10 d9 d8 t2pr 07407h d7 d6 d5 d4 d3 d2 d1 d0 t2pr 07408h free soft tmode2 tmode1 tmode0 tps2 tps1 tps0 t2con 07408h tswt1 tenable tclks1 tclks0 tcld1 tcld0 tecmpr selt1pr t2con 07409h d15 d14 d13 d12 d11 d10 d9 d8 t3cnt 07409h d7 d6 d5 d4 d3 d2 d1 d0 t3cnt 0740ah d15 d14 d13 d12 d11 d10 d9 d8 t3cmpr 0740ah d7 d6 d5 d4 d3 d2 d1 d0 t3cmpr 0740bh d15 d14 d13 d12 d11 d10 d9 d8 t3pr 0740bh d7 d6 d5 d4 d3 d2 d1 d0 t3pr 0740ch free soft tmode2 tmode1 tmode0 tps2 tps1 tps0 t3con 0740ch tswt1 tenable tclks1 tclks0 tcld1 tcld0 tecmpr selt1pr t3con 0740dh to 07410h reserved full and simple compare unit registers 07411h cenable cld1 cld0 svenable actrld1 actrld0 fcompoe scompoe comcon 07411h seltmr scld1 scld0 sactrld1 sactrld0 selcmp3 selcmp2 selcmp1 comcon 07412h reserved 07413h svrdir d2 d1 d0 cmp6act1 cmp6act0 cmp5act1 cmp5act0 actr 07413h cmp4act1 cmp4act0 cmp3act1 cmp3act0 cmp2act1 cmp2act0 cmp1act1 cmp1act0 actr e e e e e e e e 07414h e e scmp3- act1 scmp3- act0 scmp2- act1 scmp2- act0 scmp1- act1 scmp1- act0 sactr 07415h dbt7 dbt6 dbt5 dbt4 dbt3 dbt2 dbt1 dbt0 dbtcon 07415h edbt3 edbt2 edbt1 dbtps1 dbtps0 e e e dbtcon 07416h reserved 07417h d15 d14 d13 d12 d11 d10 d9 d8 cmpr1 07417h d7 d6 d5 d4 d3 d2 d1 d0 cmpr1 07418h d15 d14 d13 d12 d11 d10 d9 d8 cmpr2 07418h d7 d6 d5 d4 d3 d2 d1 d0 cmpr2 07419h d15 d14 d13 d12 d11 d10 d9 d8 cmpr3 07419h d7 d6 d5 d4 d3 d2 d1 d0 cmpr3 0741ah d15 d14 d13 d12 d11 d10 d9 d8 scmpr1 0741ah d7 d6 d5 d4 d3 d2 d1 d0 scmpr1 0741bh d15 d14 d13 d12 d11 d10 d9 d8 scmpr2 0741bh d7 d6 d5 d4 d3 d2 d1 d0 scmpr2 0741ch d15 d14 d13 d12 d11 d10 d9 d8 scmpr3 0741ch d7 d6 d5 d4 d3 d2 d1 d0 scmpr3 0741dh to 0741fh reserved
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 102 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 capture unit registers 07420h capres capqepn cap3en cap4en cap34tsel cap12tsel cap4toadc capcon 07420h cap1edge cap2edge cap3edge cap4edge capcon 07421h reserved 07422h cap4fifo cap3fifo cap2fifo cap1fifo capfifo 07422h capfifo15 capfifo14 capfifo13 capfifo12 capfifo11 capfifo10 capfifo9 capfifo8 capfifo 07423h d15 d14 d13 d12 d11 d10 d9 d8 cap1fifo 07423h d7 d6 d5 d4 d3 d2 d1 d0 cap1fifo 07424h d15 d14 d13 d12 d11 d10 d9 d8 cap2fifo 07424h d7 d6 d5 d4 d3 d2 d1 d0 cap2fifo 07425h d15 d14 d13 d12 d11 d10 d9 d8 cap3fifo 07425h d7 d6 d5 d4 d3 d2 d1 d0 cap3fifo 07426h d15 d14 d13 d12 d11 d10 d9 d8 cap4fifo 07426h d7 d6 d5 d4 d3 d2 d1 d0 cap4fifo 07427h to 0742bh reserved event manager (ev) interrupt control registers 0742ch e e e e e t1ofint ena t1ufint ena t1cint ena evimra 0742ch t1pint ena scmp3int ena scmp2int ena scmp1int ena cmp3int ena cmp2int ena cmp1int ena pdpint ena evimra e e e e e e e e 0742dh t3ofint ena t3ufint ena t3cint ena t3pint ena t2ofint ena t2ufint ena t2cint ena t2pint ena evimrb e e e e e e e e 0742eh e e e e cap4int ena cap3int ena cap2int ena cap1int ena evimrc 0742fh e e e e e t1ofint flag t1ufint flag t1cint flag evifra 0742fh t1pint flag scmp3int flag scmp2int flag scmp1int flag cmp3int flag cmp2int flag cmp1int flag pdpint flag evifra e e e e e e e e 07430h t3ofint flag t3ufint flag t3cint flag t3pint flag t2ofint flag t2ufint flag t2cint flag t2pint flag evifrb e e e e e e e e 07431h e e e e cap4int flag cap3int flag cap2int flag cap1int flag evifrc 07432h 0 0 0 0 0 0 0 0 evivra 07432h 0 0 d5 d4 d3 d2 d1 d0 evivra 07433h 0 0 0 0 0 0 0 0 evivrb 07433h 0 0 d5 d4 d3 d2 d1 d0 evivrb 07434h 0 0 0 0 0 0 0 0 evivrc 07434h 0 0 d5 d4 d3 d2 d1 d0 evivrc 07435h to 0743fh reserved
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 103 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 20. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o memory space flash control mode register 2 0ff0fh e e e e e e e e fcmr 0ff0fh e e e e e e e e fcmr wait-state generator control register 0ffffh e e e e e e e e wsgr 0ffffh e e e e avis isws dsws psws wsgr 2 see the flash control mode register section.
tms320c240, tms320f240 dsp controllers sprs042d october 1996 revised november 1998 104 post office box 1443 ? houston, texas 772511443 mechanical data pq (s-pqfp-g***) plastic quad flatpack 100 lead shown 88 0.012 (0,30) 0.008 (0,20) 64 0.025 (0,635) seating plane 132 1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045 / c 11/95 100 1 13 63 39 od2o sq od1o sq odo sq 14 od3o sq 38 dim odo od2o od3o od1o nom min max min max min max leads *** 0.180 (4,57) max 100 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) m 0.006 (0,15) 0.010 (0,25) 0.020 (0,51) min 0.130 (3,30) 0.150 (3,81) 0.006 (0,16) nom gage plane 0.036 (0,91) 0.046 (1,17) 0 8 89 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec mo-069
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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